ICE: incremental 3-dimensional capacitance and resistance extraction for an iterative design environment
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[1] Prithviraj Banerjee,et al. A Parallel 3-D Capacitance Extraction Program , 1999, HiPC.
[2] Prithviraj Banerjee,et al. Compiler support for hybrid irregular accesses on multicomputers , 1996, ICS '96.
[3] Mahmut T. Kandemir,et al. A hyperplane based approach for optimizing spatial locality in loop nests , 1998, ICS '98.
[4] Majid Sarrafzadeh,et al. Power Optimization of Delay Constrained Circuits , 2000, VLSI Design.
[5] Janak H. Patel,et al. A parallel algorithm for fault simulation based on PROOFS , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[6] Rajesh Gupta,et al. Implications of VHDL timing models on simulation and software synthesis , 1997, J. Syst. Archit..
[7] Prithviraj Banerjee,et al. Actor based parallel VHDL simulation using time warp , 1996, Workshop on Parallel and Distributed Simulation.
[8] Prithviraj Banerjee,et al. A C compiler for a processor with a reconfigurable functional unit , 2000, FPGA '00.
[9] Alok Choudhary,et al. OVERVIEW OF THE MATCH COMPILER FOR COMPILING MATLAB PROGRAMS INTO HARDWARE , 2001 .
[10] Dilip Krishnaswamy,et al. Exploiting task and data parallelism in parallel Hough and Radon transforms , 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).
[11] Mahmut T. Kandemir,et al. Efficient synthesis of array intensive computations onto FPGA based accelerators , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[12] Prithviraj Banerjee,et al. Parallel Logic Synthesis Using Partitioning , 1994, 1994 International Conference on Parallel Processing Vol. 3.
[13] Prithviraj Banerjee,et al. Techniques to overlap computation and communication in irregular iterative applications , 1994, ICS '94.
[14] Prithviraj Banerjee,et al. Parallel compiled event driven VHDL simulation , 1998, ICS '98.
[15] Mahmut T. Kandemir,et al. Minimizing Data and Synchronization Costs in One-Way Communication , 2000, IEEE Trans. Parallel Distributed Syst..
[16] Prithviraj Banerjee,et al. Integrating task and data parallelism in an irregular application: a case study , 1996, Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing.
[17] Mahmut T. Kandemir,et al. On reducing false sharing while improving locality on shared memory multiprocessors , 1999, 1999 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00425).
[18] Alok N. Choudhary,et al. An efficient uniform run-time scheme for mixed regular-irregular applications , 1998, ICS '98.
[19] Kapur,et al. IES/sup 3/: a fast integral equation solver for efficient 3-dimensional extraction , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[20] Prithviraj Banerjee,et al. A parallel algorithm for timing-driven global routing for standard cells , 1998, Proceedings. 1998 International Conference on Parallel Processing (Cat. No.98EX205).
[21] Elizabeth M. Rudnick,et al. Sequential circuit testability enhancement using a nonscan approach , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[22] Amber Roy-Chowdhury,et al. A New Error Analysis Based Method for Tolerance Computation for Algorithm-Based Checks , 1996, IEEE Trans. Computers.
[23] Alok N. Choudhary,et al. A system for synthesizing optimized FPGA hardware from Matlab(R) , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[24] Alok N. Choudhary,et al. Parallel algorithms for FPGA placement , 2000, ACM Great Lakes Symposium on VLSI.
[25] Prithviraj Banerjee,et al. Load balancing and work load minimization of overlapping parallel tasks , 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).
[26] Prithviraj Banerjee,et al. Efficient equivalence checking of multi-phase designs using retiming , 1998, ICCAD '98.
[27] Amber Roy-Chowdhury,et al. Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems , 1996, IEEE Trans. Computers.
[28] Prithviraj Banerjee,et al. Accurate Data and Context Management in Message-Passing Programs , 1999, LCPC.
[29] Alok N. Choudhary,et al. Parallelization of MATLAB Applications for a Multi-FPGA System , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).
[30] Prithviraj Banerjee,et al. A parallel implementation of a fast multipole based 3-D capacitance extraction program on distributed memory multicomputers , 2000, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000.
[31] Mahmut T. Kandemir,et al. A Layout-Conscious Iteration Space Transformation Technique , 2001, IEEE Trans. Computers.
[32] Prithviraj Banerjee,et al. Evaluation of compiler and runtime library approaches for supporting parallel regular applications , 1998, Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing.
[33] Carlos Alberto Brebbia,et al. The Boundary Element Method for Engineers , 1978 .
[34] Sachin S. Sapatnekar,et al. A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers , 1994 .
[35] Mahmut T. Kandemir,et al. A Matrix-Based Approach to Global Locality Optimization , 1999, J. Parallel Distributed Comput..
[36] Mahmut Kandemir,et al. An Iteration Space Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality , 1999 .
[37] Mahmut T. Kandemir,et al. A framework for interprocedural locality optimization using both loop and data layout transformations , 1999, Proceedings of the 1999 International Conference on Parallel Processing.
[38] Prithviraj Banerjee,et al. Performance evaluation of a C++ library based multithreaded system , 1997, Proceedings of the Thirtieth Hawaii International Conference on System Sciences.
[39] S. Roy,et al. PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[40] John A. Chandy,et al. A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement , 1999, J. Parallel Distributed Comput..
[41] Prithviraj Banerjee,et al. A novel compilation framework for supporting semi-regular distributions in hybrid applications , 1999, Proceedings 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. IPPS/SPDP 1999.
[42] John A. Chandy,et al. Communication Optimizations Used in the Paradigm Compiler for Distributed-Memory Multicomputers , 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.
[43] Amber Roy-Chowdhury,et al. A Fault-Tolerant Parallel Algorithm for Iterative Solution of the Laplace Equation , 1993, 1993 International Conference on Parallel Processing - ICPP'93.
[44] Prithviraj Banerjee,et al. Parallel algorithms for power estimation , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[45] Prithviraj Banerjee,et al. Computing Array Shapes in MATLAB , 2001, LCPC.
[46] Prithviraj Banerjee,et al. Software schemes of reconfiguration and recovery in distributed memory multicomputers using the actor model , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[47] Alok N. Choudhary,et al. FPGA hardware synthesis from MATLAB , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[48] Rajesh Gupta,et al. A procedure for software synthesis from VHDL models , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.
[49] Prithviraj Banerjee,et al. PARADIGM (version 2.0): a new HPF compilation system , 1999, Proceedings 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. IPPS/SPDP 1999.
[50] Jonathan Rose. Parallel global routing for standard cells , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[51] Mahmut T. Kandemir,et al. A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts , 1999, IEEE Trans. Parallel Distributed Syst..
[52] P. Banerjee,et al. Parallel construction algorithms for BDDs , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[53] Prithviraj Banerjee,et al. Compiler and Run-Time Support for Exploiting Regularity within Irregular Applications , 2000, IEEE Trans. Parallel Distributed Syst..
[54] Prithviraj Banerjee,et al. Correctly detecting intrinsic type errors in typeless languages such as MATLAB , 2000, APL '01.
[55] Andreas Moshovos,et al. CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.
[56] Prithviraj Banerjee,et al. Comparative study of parallel algorithms for 3-D capacitance extraction on distributed memory multiprocessors , 2000, Proceedings 2000 International Conference on Computer Design.
[57] Prithviraj Banerjee,et al. Global optimization techniques for automatic parallelization of hybrid applications , 2001, ICS '01.
[58] Prithviraj Banerjee,et al. Compiler support for privatization on distributed-memory machines , 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.
[59] Prithviraj Banerjee,et al. Processor Tagged Descriptors: A Data Structure for Compiling for Distributed-Memory Multicomputers , 1994, IFIP PACT.
[60] John A. Chandy,et al. The Paradigm Compiler for Distributed-Memory Multicomputers , 1995, Computer.
[61] Alok N. Choudhary,et al. Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB , 2000, CASES '00.
[62] Prithviraj Banerjee,et al. Automatic Selection of Dynamic Data Partitioning Schemes for Distributed-Memory Multicomputers , 1995, LCPC.
[63] John A. Chandy,et al. WADE: a Web-based automated parallel CAD environment , 1998, Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238).
[64] Prithviraj Banerjee,et al. Parallel Algorithms for VLSI Layout Verification , 1996, J. Parallel Distributed Comput..
[65] Alok N. Choudhary,et al. An algorithm for synthesis of large time-constrained heterogeneous adaptive systems , 2001, TODE.
[66] Sachin S. Sapatnekar,et al. A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers , 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.
[67] Janak H. Patel,et al. ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation , 1994, 31st Design Automation Conference.
[68] Elizabeth M. Rudnick,et al. SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[69] Weiping Shi,et al. A fast hierarchical algorithm for 3-D capacitance extraction , 1998, DAC.
[70] Alok N. Choudhary,et al. Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[71] Majid Sarrafzadeh,et al. POWER OPTIMIZATION ISSUES IN DUAL VOLTAGE , 2000 .
[72] Prithviraj Banerjee,et al. An L-shaped partitioning-based algebraic factorization algorithm , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[73] Prithviraj Banerjee,et al. Optimizations for Efficient Array Redistribution on Distributed Memory Multicomputers , 1996, J. Parallel Distributed Comput..
[74] Prithviraj Banerjee,et al. A portable parallel algorithm for logic synthesis using transduction , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[75] Kaushik De. Parallel algorithms for logic synthesis , 1993 .
[76] David E. Long,et al. IES3: a fast integral equation solver for efficient 3-dimensional extraction , 1997, ICCAD.
[77] Prithviraj Banerjee,et al. A parallel algorithm for zero skew clock tree routing , 1998, ISPD '98.
[78] Prithviraj Banerjee,et al. A low-power logic optimization methodology based on a fast power-driven mapping , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).
[79] John A. Chandy,et al. Distributed Object Oriented Data Structures and Algorithms for VLSI CAD , 1996, IRREGULAR.
[80] Alok N. Choudhary,et al. A system-level synthesis algorithm with guaranteed solution quality , 2000, DATE '00.
[81] Prithviraj Banerjee,et al. Compiling MATLAB programs to ScaLAPACK: exploiting task and data parallelism , 1996, Proceedings of International Conference on Parallel Processing.
[82] Prithviraj Banerjee,et al. Simulated Annealing Based Parallel State Assignment of Finite State Machines , 1997, J. Parallel Distributed Comput..
[83] Prithviraj Banerjee,et al. Algorithm-Based Error Detection Schemes for Iterative Solution of Partial Differential Equations , 1996, IEEE Trans. Computers.
[84] Mahmut T. Kandemir,et al. Improving locality using loop and data transformations in an integrated framework , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.
[85] R. Saleh. FastCap : A Multipole Accelerated 3-D Capacitance Extraction Program , 1991 .
[86] Mahmut T. Kandemir,et al. A global communication optimization technique based on data-flow analysis and linear algebra , 1999, TOPL.
[87] Mahmut T. Kandemir,et al. A matrix-based approach to the global locality optimization problem , 1998, Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192).
[88] Prithviraj Banerjee,et al. ProperCAD: a portable object-oriented parallel environment for VLSI CAD , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[89] Majid Sarrafzadeh,et al. Placement with Incomplete Data , 1999, VLSI Design.
[90] Prithviraj Banerjee,et al. A comparison of parallel approaches for algebraic factorization in logic synthesis , 1997, Proceedings 11th International Parallel Processing Symposium.
[91] Majid Sarrafzadeh,et al. Partitioning sequential circuits for low power , 1998, Proceedings Eleventh International Conference on VLSI Design.
[92] Vamsi Boppana,et al. A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs , 1996, Euro-Par, Vol. I.
[93] Kaushik De,et al. Fine-grained parallel VLSI synthesis for commercial CAD on a network of workstations , 2000, Proceedings 2000 International Conference on Parallel Processing.
[94] Michael S. Hsiao,et al. Parallel genetic algorithms for simulation-based sequential circuit test generation , 1997, Proceedings Tenth International Conference on VLSI Design.
[95] Alok N. Choudhary,et al. Match virtual machine: an adaptive runtime system to execute MATLAB in parallel , 2000, Proceedings 2000 International Conference on Parallel Processing.
[96] Prithviraj Banerjee,et al. Compilation of scientific programs into multithreaded and message driven computation , 1994, Proceedings of IEEE Scalable High Performance Computing Conference.
[97] M. Guptay,et al. Compile-Time Estimation of Communication Costs ofPrograms , 1994 .
[98] Prithviraj Banerjee,et al. Handling context-sensitive syntactic issues in the design of a front-end for a MATLAB compiler , 2000, APL '00.
[99] Sungho Kim,et al. An evaluation of parallel simulated annealing strategies with application to standard cell placement , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[100] Prithviraj Banerjee,et al. An implicit algorithm for finding steady states and its application to FSM verification , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[101] John A. Chandy,et al. An Overview of the Paradigm Compiler for Distributed-memory Multicomputers , 1995 .
[102] Prithviraj Banerjee,et al. A parallel hierarchical algorithm for module placement based on sparse linear equations [VLSI layout] , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[103] J. Ramanujam,et al. Enhancing Spatial Locality using Data Layout Optimizations , 1997 .
[104] Sungho Kim,et al. ProperPLACE: a portable parallel algorithm for standard cell placement , 1994, Proceedings of 8th International Parallel Processing Symposium.
[105] Amber Roy-Chowdhury,et al. Compiler-assisted generation of error-detecting parallel programs , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.
[106] Prithviraj Banerjee,et al. An efficient assertion checker for combinational properties , 1997, DAC.
[107] Prithviraj Banerjee,et al. Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs , 1999, IEEE Trans. Computers.
[108] Zeyi Wang,et al. A two-dimensional resistance simulator using the boundary element method , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[109] Shin Nakamura,et al. A ULSI 2-D capacitance simulator for complex structures based on actual processes , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[110] Suku Nair,et al. Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes , 1996, IEEE Trans. Computers.
[111] Amber Roy-Chowdhury,et al. Algorithm-based fault location and recovery for matrix computations , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.
[112] John A. Chandy,et al. Parallel simulated annealing strategies for VLSI cell placement , 1996, Proceedings of 9th International Conference on VLSI Design.
[113] Prithviraj Banerjee,et al. Simultaneous Allocation and Scheduling Using Convex Programming Techniques , 1995, Parallel Process. Lett..
[114] Mahmut T. Kandemir,et al. A generalized framework for global communication optimization , 1998, Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing.
[115] Prithviraj Banerjee,et al. Simultaneous scheduling, binding and floorplanning in high-level synthesis , 1998, Proceedings Eleventh International Conference on VLSI Design.
[116] Prithviraj Banerjee,et al. A parallel algorithm for state assignment of finite state machines , 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.
[117] Alok N. Choudhary,et al. Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB(R) , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).
[118] M. Kandemir,et al. An ILP Approach for Optimizing Cache Locality , 1998 .
[119] Prithviraj Banerjee,et al. The Efficient Computation of Ownership Sets in HPF , 2001, IEEE Trans. Parallel Distributed Syst..
[120] Prithviraj Banerjee,et al. ProperTEST: a portable parallel test generator for sequential circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[121] Prithviraj Banerjee,et al. PowerShake: a low power driven clustering and factoring methodology for Boolean expressions , 1998, Proceedings Design, Automation and Test in Europe.
[122] G. Ramalingam. Bounded Incremental Computation , 1996, Lecture Notes in Computer Science.
[123] Majid Sarrafzadeh,et al. Simultaneous scheduling, binding and floorplanning for interconnect power optimization , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).
[124] Mahmut T. Kandemir,et al. A graph based framework to detect optimal memory layouts for improving data locality , 1999, Proceedings 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. IPPS/SPDP 1999.
[125] Prithviraj Banerjee,et al. An α-approxmimate algorithm for delay-constraint technology mapping , 1999, DAC '99.
[126] Prithviraj Banerjee,et al. Automatic generation of efficient array redistribution routines for distributed memory multicomputers , 1995, Proceedings Frontiers '95. The Fifth Symposium on the Frontiers of Massively Parallel Computation.
[127] John A. Chandy,et al. A library-based approach to portable, parallel, object-oriented programming: interface, implementation, and application , 1994, Proceedings of Supercomputing '94.
[128] Prithviraj Banerjee,et al. Efficient equivalence checking of multi-phase designs using phase abstraction and retiming , 1998, TODE.
[129] Prithviraj Banerjee,et al. Dynamic Data Partitioning for Distributed-Memory Multicomputers , 1996, J. Parallel Distributed Comput..
[130] Sumit Roy,et al. Resynthesis of sequential circuits for low power , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[131] Prithviraj Banerjee,et al. Incremental capacitance extraction and its application to iterative timing-driven detailed routing , 1999, ISPD '99.
[132] Prithviraj Banerjee,et al. Exploiting spatial regularity in irregular iterative applications , 1995, Proceedings of 9th International Parallel Processing Symposium.
[133] John A. Chandy,et al. Performance evaluation of message-driven parallel VLSI CAD applications on general purpose multiprocessors , 1997, ICS '97.
[134] Prithviraj Banerjee,et al. Interprocedural Array Redistribution Data-Flow Analysis , 1996, LCPC.
[135] Prithviraj Banerjee,et al. RSYN: a system for automated synthesis of reliable multilevel circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..