Defect-Tolerant CMOL Memories

We have calculated the useful bit density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective crossbar nanoelectronic memories, as a function of the defective memory cell fraction. While our calculations are based on a particular (“CMOL”) memory matrix topology, with an area-distributed nano/CMOS interface and naturally segmented nanowires, for realistic parameters our results are also applicable to “global” crossbar memory matrices with peripheral interfaces. The results indicate that the crossbar memories with a nano/CMOS pitch ratio close to 1/3 (which is typical for the current, initial stage of the nanoelectronics development), may overcome purely semiconductor memories in useful bit density if the fraction of bad nanodevices is below ∼ 15%, even under rather tough (30 ns) restrictions on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the crosspoint memories may be far superior to the densest semiconductor memories by providing, e. g., a 1 Tbit/cm 2 density even for a plausible defect fraction of 2%. These highly encouraging results are much better that those reported in literature earlier, including our own early work.

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