A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.

[1]  Robert G. Meyer,et al.  Relationship between frequency response and settling time of operational amplifiers , 1974 .

[2]  Andrea Baschirotto,et al.  A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulator with 74-dB dynamic range , 2001 .

[3]  T. Fiez,et al.  Effect of switch resistance on the SC integrator settling time , 1999 .

[4]  Jose Silva-Martinez,et al.  A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors , 2003, IEEE J. Solid State Circuits.

[5]  B.A. Wooley,et al.  A two-path bandpass /spl Sigma//spl Delta/ modulator for digital IF extraction at 20 MHz , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[6]  José Silva-Martínez,et al.  A 92MHz, 80dB peak SNR SC bandpass /spl Sigma//spl Delta/ modulator based on a high GBW OTA with no Miller capacitors in 0.35/spl mu/m CMOS technology , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[7]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[8]  Bruce A. Wooley,et al.  A two-path bandpass ΣΔ modulator for digital IF extraction at 20 MHz , 1997 .

[9]  V.S.L. Cheung,et al.  A 1 V 10.7 MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using doublesampling finite-gain-compensation technique , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[10]  T. Fiez,et al.  Settling time design considerations for SC integrators , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[11]  Saska Lindfors,et al.  80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers , 2003 .

[12]  Shen-Iuan Liu,et al.  A double-sampling pseudo-two-path bandpass /spl Delta//spl Sigma/ modulator , 2000, IEEE Journal of Solid-State Circuits.

[13]  Howard C. Luong,et al.  A 1V 10.7MHz switched-opamp bandpass ∑Δ modulator using double- sampling finite-gain-compensation technique , 2001 .

[14]  V.S.L. Cheung,et al.  A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques , 2005, IEEE Journal of Solid-State Circuits.