Isolation Techniques in Power ICs with Vertical Current Flow

Thie inrlulease iif Lthe uara-ge of applicaLions of today's ICs is direcLly ielated to the fabrication of devices whicih cant buLo i tisl Larld Ihighler vol Lages arid hiarndle lar:ger curr[eentsL Thiis cari be accomplished eiLher by i ipirovilrig the peirformances of Loie starndard ICs, or' by uilizirig i rnLel 1igentL power Ltrans is Lors, e.g. moiurroI i thiicall y in tegratinig the power stage arid a low vol Lage contLrol circoi1 try.f To uperaL o ucssfully ir3 Ltle iigii VoI L*Aiiper e r arige-, Lthe powestLage mi;usL hiave a vertLical cutrruentL flow arid is Lherefor1e bui1L orn lightLly duped r-Ltype layer.s. It is possible Lto el i zr e v*eriL cal power stages wi thi eiitLhera siLI g le inluatLed collectLor (or draini) LrLanisis 5'tor, or wi Lliiianiy Lranisis tors sharinlg a collilliol collecLor (draini.) Trhe ve tLical curreriL flow alloLws thie bet expioL';itaiofi of' thre Si ar-ea, sinice !L a imliztesLile :urrntL deisitLy, uilike Lhe stanidad lCs, whiere thie cur'rietlL filow makes a ti-toun. Figure 1 sIhows Lte di fferrnce betweeni Lhe wo 6tutul-eb,e T ie Lec iniology de su ibed inr this p. reL d ve nt ge o thie better per forniarices of the vetLtical sri-ucuru-e tL 'ari s or togeLther with L Lle we1l knowrn low uobLt rid designi flexibiliLy of stanidard bipolar ICs.