Reconfigurable Elliptic Curve Crypto-Hardware Over the Galois Field GF(2163)

Problem statement: In the last decade, many hardware designs of elliptic curves cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field Programmable Gate Arrays (FPGA), the major issue concerned the ability of embedding this strategic and strong algorithm in a very few hardware. That is, finding an optimal solution to the one to many problem: Portability against power consumption, speed against area and maintaining security at its highest level. Our strategy is to hardware execute the ECC algorithm that reposes on the ability of making the scalar multiplication over the GF(2163) in a restricted number of clock cycles, targeting the acceleration of the basic field operations, mainly the multiplication and the inverse process, under the constraint of hardware optimization. Approach: The research was based on using the efficient Montgomery add and double algorithm, the Karatsuba-Offman multiplier and the Itoh-Tsjuii algorithm for the inverse component. The hardware implementation was based upon an optimized Finite State Machine (FSM), with a single cycle 163 bits multiplier and a script generated field squarer. The main characteristics of the design concerned the elimination of the different internal component to component delays, the minimization of the global clocking resources and a strategic separation of the data path from the control part. Results: The working frequency of our design attained the 561 MHz, allowing 161786 scalar multiplications per second, outperforming one of the best state of the art implementations (555 MHz); the other contribution concerns the acceleration of the field inverse scheme with a frequency of 777.341 MHz. Conclusion: The results indicated that using different optimizations at the hardware level improve efficiently the acceleration of the ECC scalar multiplication and the choice of the target circuit gratefully enhances propagation delays and increases frequency.

[1]  Wayne Luk,et al.  Customizable elliptic curve cryptosystems , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Tim Kerins,et al.  An FPGA implementation of a GF(p) ALU for encryption processors , 2004, Microprocess. Microsystems.

[3]  Mohammed Benaissa,et al.  Design of flexible GF(2/sup m/) elliptic curve cryptography processors , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Jean-Jacques Quisquater,et al.  An improved Montgomery modular inversion targeted for efficient implementation on FPGA , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[5]  William P. Marnane,et al.  Optimised Montgomery domain inversion on FPGA , 2005, Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005..

[6]  Akashi Satoh,et al.  A Scalable Dual-Field Elliptic Curve Cryptographic Processor , 2003, IEEE Trans. Computers.

[7]  W.N. Chelton,et al.  A scalable GF(2/sup m/) arithmetic unit for application in an ECC processor , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..

[8]  Gang Quan,et al.  High-level synthesis for large bit-width multipliers on FPGAs: a case study , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[9]  Manfred Glesner,et al.  On the design of reconfigurable multipliers for integer and Galois field multiplication , 2009, Microprocess. Microsystems.

[10]  Máire O'Neill,et al.  An Adaptable And Scalable Asymmetric Cryptographic Processor , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[11]  Wei-Chang Tsai,et al.  A systolic architecture for elliptic curve cryptosystems , 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

[12]  Mohammed Benaissa,et al.  Fast Elliptic Curve Cryptography on FPGA , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Jamshid Shokrollahi,et al.  Efficient implementation of elliptic curve cryptography on FPGAs , 2006 .

[14]  Alfred Menezes,et al.  Guide to Elliptic Curve Cryptography , 2004, Springer Professional Computing.

[15]  Máire O'Neill,et al.  Hardware Elliptic Curve Cryptographic Processor Over$rm GF(p)$ , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Francisco Rodríguez-Henríquez,et al.  Cryptographic Algorithms on Reconfigurable Hardware , 2010 .

[17]  Christof Paar,et al.  Security on FPGAs: State-of-the-art implementations and attacks , 2004, TECS.

[18]  Ingrid Verbauwhede,et al.  Elliptic-Curve-Based Security Processor for RFID , 2008, IEEE Transactions on Computers.

[19]  Guido Bertoni,et al.  A parallelized design for an elliptic curve cryptosystem coprocessor , 2005, International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II.

[20]  Ingrid Verbauwhede,et al.  High-performance Public-key Cryptoprocessor for Wireless Mobile Applications , 2007, Mob. Networks Appl..

[21]  J. Milne.  Elliptic Curves , 2020 .

[22]  Christof Paar,et al.  Itoh-Tsujii Inversion in Standard Basis and Its Application in Cryptography and Codes , 2002, Des. Codes Cryptogr..

[23]  J. Teich,et al.  FPGA designs of parallel high performance GF(2/sup 233/) multipliers [cryptographic applications] , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[24]  Francisco Rodríguez-Henríquez,et al.  An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method , 2005, 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05).

[25]  Dale Husemoller.  Elliptic Curves (2nd ed.) , 2004 .