4-Bit Double SONOS Memories (DSMs) Using Single-Level and Multi-Level Cell Schemes

In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher VTH shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The VTH shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention

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