Ef3S: An evaluation framework for flash-based systems
暂无分享,去创建一个
[1] Chaitali Chakrabarti,et al. Flexible product code-based ECC schemes for MLC NAND Flash memories , 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).
[2] Paolo Prinetto,et al. Automated synthesis of EDACs for FLASH memories with user-selectable correction capability , 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).
[3] Paolo Prinetto,et al. EDACs and test integration strategies for NAND flash memories , 2010, 2010 East-West Design & Test Symposium (EWDTS).
[4] Mark G. Karpovsky,et al. Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[5] Paolo Prinetto,et al. Design Issues and Challenges of File Systems for Flash Memories , 2011 .
[6] Aviral Shrivastava,et al. FSAF: File system aware flash translation layer for NAND Flash Memories , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[7] Wei Liu,et al. VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] Hong Ding,et al. A 113mm2 32Gb 3b/cell NAND flash memory , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[9] Youngjae Kim,et al. FlashSim: A Simulator for NAND Flash-Based Solid-State Drives , 2009, 2009 First International Conference on Advances in System Simulation.
[10] David Woodhouse,et al. JFFS : The Journalling Flash File System , 2001 .
[11] Paolo Prinetto,et al. Design and optimization of adaptable BCH codecs for NAND flash memories , 2013, Microprocess. Microsystems.
[12] Zhongfeng Wang,et al. Error correction for multi-level NAND flash memory using Reed-Solomon codes , 2008, 2008 IEEE Workshop on Signal Processing Systems.
[13] Da-Wei Chang,et al. ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation , 2011, IEEE Transactions on Computers.
[14] Wonyong Sung,et al. A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).
[15] Tong Zhang,et al. On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[16] Massimo Rossini,et al. A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[17] Paolo Prinetto,et al. A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[18] J. Kessenich,et al. Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.