Data transmission and diagnosis in bus networks derived from block design

This paper presents a method for constructing bus networks interconnecting a large number of data processors based on the block design. Properties of the bus networks constructed, an algorithm for finding data routing paths, and conditions for a distributed diagnostic procedure are presented. In the construction method considered, we regard a block and an object in the block design as a processor and a bus, respectively. Then two processors are either connected to the same bus or interconnected via a single intermediate processor. There are almost as many such independent data routing paths through a single intermediate processor as I/O ports of a processor. In fault diagnosis it is a general practice to assume an upper bound on the number of failed processors. For our bus network, we can show that it is possible to diagnose all the processors correctly by a distributed diagnostic method if the number of failed processors is less than min(n/2, d), where n is the number of processors and, with q and m denoting the number of I/O ports per processor and of buses, respectively, d = 4(m - q)/q (q: even) or d = 4q(m - q)/(q2 - 1) (q: odd).

[1]  James E. Smith,et al.  Diagnosis of Systems with Asymmetric Invalidation , 1981, IEEE Transactions on Computers.

[2]  Marvin H. Solomon,et al.  Processor Interconnection Strategies , 1980, IEEE Transactions on Computers.

[3]  S. Louis Hakimi,et al.  On Adaptive System Diagnosis , 1984, IEEE Transactions on Computers.

[4]  James E. Smith,et al.  Self-Diagnosis in Distributed Systems , 1985, IEEE Transactions on Computers.

[5]  Jean-Claude Bermond,et al.  Surveys in Combinatorics: GRAPHS AND INTERCONNECTION NETWORKS: DIAMETER AND VULNERABILITY , 1983 .

[6]  Larry D. Wittie,et al.  Communication Structures for Large Networks of Microcomputers , 1981, IEEE Transactions on Computers.

[7]  Ming T. Liu,et al.  A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems , 1981, IEEE Transactions on Computers.

[8]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[9]  Dhiraj K. Pradhan,et al.  Fault-Tolerant Multiprocessor Link and Bus Network Architectures , 1994, IEEE Transactions on Computers.

[10]  GERNOT METZE,et al.  On the Connection Assignment Problem of Diagnosable Systems , 1967, IEEE Trans. Electron. Comput..