Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers

An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm/sup 2/ 62M transistor IC is implemented in foundry portable 0.18/spl mu/m CMOS technology.

[1]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  William J. Dally,et al.  Digital Systems Engineering: TIMING CONVENTIONS , 1998 .

[3]  William J. Dally,et al.  Digital systems engineering , 1998 .

[4]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997 .