High-speed highly sensitive CMOS image sensors

The demand on high-speed CMOS image sensor (CIS) becomes higher in recent years. They are important for a wide range of applications, such as radiography, particle detection, sports, mechanical diagnosis, robot guidance, security surveillance and bio-medical research. High sensitivity is required in high-speed CISs as the exposure time is short. CISs with conventional pixels have low sensitivities due to the large photodiode capacitor. Image lag is evident with the traditional lateral charge transfer gate especially under low illumination. Also, the column parallel analog-to-digital converter (ADC) arrays in existing CISs have either low resolution or large area. In this thesis, two CISs with capacitive transimpedance amplifier (CTIA) pixels are developed to enhance the imaging speed and sensitivity simultaneously. Novel columnparallel successive approximation register (SAR) ADCs are designed to reduce the area of column quantization circuits significantly. A 1500 fps 256×256 CIS is designed in a 0.18-μm mixed-signal CMOS process for micro-CT. A tiny metal-oxide-metal (MOM) integration capacitor (CINT) is used in the CTIA pixel to achieve the high sensitivity. To compensate the CINT mismatches across the pixel array, an on-chip calibration scheme is developed. After calibration, a low fixed-pattern noise (FPN) of 0.52% can be achieved. With the white light illumination, the sensitivity is measured to be 68.5V/lux·s, which is higher than the previous highest CIS by 240%. The CIS also has low temporal noise (13.6erms). Its dynamic range is 56.5 dB. Minimum-size metalinsulator-metal (MIM) unit capacitors are used to implement the capacitor array of the SAR ADC. A digital calibration method based on dithering is devised to compensate the capacitor mismatches without any analog overhead. As a result, the size of a single SAR ADC is only

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