Pushing the Limits Further: Sub-Atomic AES

While throughput has for a long time been the main focus of optimisation, the need for compact and lightweight implementations of cryptographic primitives is on the rise again. Along with development of new tailored primitives and standards, the search for small implementations of the Advanced Encryption Standard has gained momentum again. This culminated in the recent publication of the AtomicAES architecture by Banik et al., who reported a design size of just over 2000 GE. In this work we design a new 8-bit serial architecture from scratch that enables us to push the area requirement for a fully featured AES primitive further down by more than 10% of the theoretical gap left by AtomicAES for optimisation. Moreover our architecture provides full functionality for encryption and decryption including keyschedule.

[1]  Anne Canteaut,et al.  PRINCE - A Low-Latency Block Cipher for Pervasive Computing Applications - Extended Abstract , 2012, ASIACRYPT.

[2]  David Canright,et al.  A Very Compact S-Box for AES , 2005, CHES.

[3]  Matthew J. B. Robshaw,et al.  The Block Cipher Companion , 2011, Information Security and Cryptography.

[4]  Nidhi Goel,et al.  FPGA implementation of an optimized 8-bit AES architecture: A masked S-Box and pipelined approach , 2015, 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).

[5]  Kazuhiko Minematsu,et al.  $\textnormal{\textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms , 2012, Selected Areas in Cryptography.

[6]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[7]  Kyoji Shibutani,et al.  Midori: A Block Cipher for Low Energy , 2015, ASIACRYPT.

[8]  Kyoji Shibutani,et al.  Piccolo: An Ultra-Lightweight Blockcipher , 2011, CHES.

[9]  Jason Smith,et al.  The SIMON and SPECK Families of Lightweight Block Ciphers , 2013, IACR Cryptol. ePrint Arch..

[10]  Yee Wei Law,et al.  KLEIN: A New Family of Lightweight Block Ciphers , 2010, RFIDSec.

[11]  Sanu Mathew,et al.  340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS , 2015, IEEE Journal of Solid-State Circuits.

[12]  Panu Hämäläinen,et al.  Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[13]  Dongdai Lin,et al.  RECTANGLE: A Bit-slice Ultra-Lightweight Block Cipher Suitable for Multiple Platforms , 2014, IACR Cryptol. ePrint Arch..

[14]  Anne Canteaut,et al.  PRINCE - A Low-latency Block Cipher for Pervasive Computing Applications (Full version) , 2012, IACR Cryptol. ePrint Arch..

[15]  Thomas Peyrin,et al.  The LED Block Cipher , 2011, IACR Cryptol. ePrint Arch..

[16]  Matthew J. B. Robshaw,et al.  PRINTcipher: A Block Cipher for IC-Printing , 2010, CHES.

[17]  Christophe De Cannière,et al.  KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers , 2009, CHES.

[18]  Vincent Rijmen,et al.  AES implementation on a grain of sand , 2005 .

[19]  Christof Paar,et al.  Pushing the Limits: A Very Compact and a Threshold Implementation of AES , 2011, EUROCRYPT.

[20]  Mohamed Hashem,et al.  Lightweight mix columns implementation for AES , 2009 .

[21]  Markus S. Wamser Ultra-Small Designs for Inversion-Based S-Boxes , 2014, 2014 17th Euromicro Conference on Digital System Design.

[22]  Andrey Bogdanov,et al.  Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core , 2016, INDOCRYPT.

[23]  Andrey Bogdanov,et al.  Atomic-AES v 2.0 , 2016, IACR Cryptol. ePrint Arch..

[24]  Kyoji Shibutani,et al.  Midori: A Block Cipher for Low Energy (Extended Version) , 2015, IACR Cryptol. ePrint Arch..

[25]  Sandra Dominikus,et al.  Efficient AES Implementations on ASICs and FPGAs , 2004, AES Conference.

[26]  Akashi Satoh,et al.  A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.