A New TGC-Differential Input Stage to Modify Dynamic Comparator

As the technology rapidly scaling down, the escalating demand for higher accuracy is putting a heavy pressure to find ways to get rid of one of the major issues among present day dynamic comparators i.e. random offset voltage generation. A number of offset calibration techniques have been presented to resolve this issue. It has become an important concern to analyze these techniques for scaled down technology nodes to cop up with modern day dynamic latched comparators. In this paper, the input stage of comparator is modified for offset minimization and a better high frequency response. The proposed topology is verified by simulating in ‘Synopsys Custom-designer’ environment using 32/28 nm-integrated technology node. The simulation results shows improvement in random offset generation and delay for the common mode range of 0.6 V and low voltage supply of 0.8 V with the capability of detecting input voltage difference up to 0.5 mV over some of the recent works. The structure operates at a higher speed with a delay reduction from 113 ps to 46 ps at approximately the same energy dissipation of 50 µW/GHz at a higher frequency of 4 GHz. The results obtained from 100 samples of transient ‘Monte-Carlo simulations’ shows minimization in offset generation with 1-sigma input referenced offset of 0.38 mV at the latch stage without any digital calibration schemes saving large area. Keywords: TGC, mixed-signal, frequency response, offset calibration, mismatches Cite this Article Anurag Sharma, Gurinderpal Singh. A New TGC-Differential Input Stage to Modify Dynamic Comparator. Journal of VLSI Design Tools and Technology. 2016; 6(2): 74–85p.