Simultaneous functional-unit binding and floorplanning

As device feature size decreases, interconnection delay becomes the dominating factor of system performance. Thus it is important that accurate physical information is used during high level synthesis. In this paper, we consider the problem of simultaneously performing functional-unit binding and floorplanning. Experimental results indicate that our approach to combine binding and floorplanning is superior to the traditional approach of separating the two tasks.

[1]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[2]  Martin D. F. Wong,et al.  A New Algorithm for Floorplan Design , 1986, 23rd ACM/IEEE Design Automation Conference.

[3]  Sung-Mo Kang,et al.  Interconnection delay in very high-speed VLSI , 1991 .

[4]  Barry M. Pangrle,et al.  A grid-based approach for connectivity binding with geometric costs , 1993, ICCAD '93.

[5]  M.C. McFarland Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions , 1986, 23rd ACM/IEEE Design Automation Conference.

[6]  Daniel Gajski,et al.  Chippe: a system for constraint driven behavioral synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[8]  Alice C. Parker,et al.  3D scheduling: high-level synthesis with floorplanning , 1991, 28th ACM/IEEE Design Automation Conference.

[9]  David W. Knapp Fasolt: a program for feedback-driven data-path optimization , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Minjoong Rim,et al.  BINET: an algorithm for solving the binding problem , 1994, Proceedings of 7th International Conference on VLSI Design.

[11]  Sung-Mo Kang,et al.  Interconnection delay in very high-speed VLSI , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[12]  Hidetoshi Onodera,et al.  Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's , 1993, ICCAD.