Leakage power analysis of 25-nm double-gate CMOS devices and circuits

Leakage power and input pattern dependence of leakage for extremely scaled (L/sub eff/=25nm) double-gate (DG) circuits are analyzed, compared with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications. Unique DG device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for DG CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for DG device, considering state dependency, show that leakage currents for DG circuits are reduced by a factor of over 10/spl times/, compared with bulk-Si counterpart.

[1]  K. Roy,et al.  Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[2]  J. Bokor,et al.  FinFET-a quasi-planar double-gate MOSFET , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  E. Cartier,et al.  Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high-κ insulator: The role of remote phonon scattering , 2001 .

[4]  Ching-Te Chuang,et al.  Physical compact model for threshold voltage in short-channel double-gate devices , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[5]  Ching-Te Chuang,et al.  Scaling planar silicon devices , 2004, IEEE Circuits and Devices Magazine.

[6]  G. Groeseneken,et al.  Temperature dependence of threshold voltage in thin-film SOI MOSFETs , 1990, IEEE Electron Device Letters.

[7]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[8]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[9]  Anantha Chandrakasan,et al.  Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[10]  David J. Frank,et al.  Monte Carlo analysis of semiconductor devices: the DAMOCLES program , 1990 .

[11]  Mark C. Johnson,et al.  Leakage control with efficient use of transistor stacks in single threshold CMOS , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Masashi Horiguchi,et al.  Review and future prospects of low-voltage RAM circuits , 2003, IBM J. Res. Dev..

[13]  H. Iwai,et al.  Advanced gate dielectric materials for sub-100 nm CMOS , 2002, Digest. International Electron Devices Meeting,.

[14]  Keunwoo Kim,et al.  Double-gate CMOS: symmetrical- versus asymmetrical-gate devices , 2001 .

[15]  E.J. Nowak,et al.  Turning silicon on its edge [double gate CMOS/FinFET technology] , 2004, IEEE Circuits and Devices Magazine.

[16]  D. E. Burk,et al.  A temperature-dependent SOI MOSFET model for high-temperature application (27 degrees C-300 degrees C) , 1991 .

[17]  David J. Frank,et al.  Nanoscale CMOS , 1999, Proc. IEEE.