A CMOS interface circuit for detection of 1.2 Gb/s RZ data

This CMOS interface circuit is used in a radar system that digitizes the reflected signal by a multi-gigahertz analog-to-digital converter (ADC) employing Josephson junctions, producing a return-to-zero (RZ) differential binary stream with 2 mV peak-to-peak amplitude at 1.2 Gb/s. The interface amplifies, detects, and demultiplexes the signal, generating a parallel output with 1 V/sub pp/ amplitude at 150 Mb/s so the subsequent digital signal processor can receive and process the data reliably.