Oversampled Sigma Delta ADC decimation filter: Design techniques, challenges, tradeoffs and optimization

With the rapid developments in the IC technology and signal processing oversampled Sigma Delta (ΣΔ) ADCs have become the absolute choice among the competent data converters due to their efficient architectures and ease of implementation in VLSI technology. Their efficiency lies in the schemes to decrease area, reduce power consumption and ways to improve frequency response without putting any stress on design cost and compatibility factor. They have their own issues which need to be improved or optimized in order to run neck by neck for being compatible for the efficient designs. Decimation filter being the important block in the ΣΔ ADCs needs some improvements in some areas for meeting the demands of an efficient design. This paper presents a brief overview of ΣΔ ADCs, various techniques of decimation filter design and different architectures, design methods, and practical issues, solutions and tradeoffs.

[1]  Habib Mehrez,et al.  Low-power comb decimation filter for RF Sigma-Delta ADCs , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[2]  Hannu Tenhunen,et al.  A fifth-order comb decimation filter for multi-standard transceiver applications , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[3]  A.M. Nassar,et al.  Power efficient polyphase decomposition comb decimation filter in multi-rate telecommunication receivers , 2008, 2008 Mosharaka International Conference on Communications, Propagation and Electronics.

[4]  Sanjit K. Mitra,et al.  Simple method for compensation of CIC decimation filter , 2008 .

[5]  E. Hogenauer,et al.  An economical class of digital filters for decimation and interpolation , 1981 .

[6]  H. Aboushady,et al.  EFFICIENT POLYPHASE DECOMPOSITION OF COMB DECIMATION FILTERS , 2022 .

[7]  Alfonso Fernández-Vázquez,et al.  Maximally Flat CIC Compensation Filter: Design and Multiplierless Implementation , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Uwe Meyer-Baese,et al.  Digital Signal Processing with Field Programmable Gate Arrays , 2001 .

[9]  S. Park,et al.  Multi-stage IIR decimation filter design technique for high resolution sigma-delta A/D converters , 1992 .

[10]  H. Tenhunen,et al.  A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters , 2000 .

[11]  Yi Xie,et al.  High-speed low-power decimation filter for wideband Delta-Sigma ADC , 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

[12]  R. Hamming,et al.  Sharpening the response of a symmetric nonrecursive filter by multiple use of the same filter , 1977 .

[13]  S.K. Mitra,et al.  Efficient comb-rotated sinc (RS) decimator with sharpened magnitude response , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[14]  Gordana Jovanovic Dolecek,et al.  Application of Generalized Sharpening Technique for Two-Stage Comb Decimator Filter Design , 2013 .

[15]  Gordana Jovanovic Dolecek,et al.  Power and area efficient comb-based decimator for Sigma-Delta ADCs with high decimation factors , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[16]  Sabrina Hirsch,et al.  Digital Signal Processing A Computer Based Approach , 2016 .

[17]  Gordana Jovanovic-Dolecek,et al.  Zero-rotation-based nonrecursive comb structure , 2014, MWSCAS.

[18]  Gordana Jovanovic-Dolecek,et al.  A new cascaded modified CIC-cosine decimation filter , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[19]  Lara Dolecek,et al.  Novel multiplierless wide-band CIC compensator , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[20]  Lars Wanhammar,et al.  Power estimation of recursive and non-recursive CIC filters implemented in deep-submicron technology , 2010, The 2010 International Conference on Green Circuits and Systems.

[21]  H. Aboushady,et al.  Efficient polyphase decomposition of comb decimation filters in /spl Sigma//spl utri/ analog-to-digital converters , 2001 .

[22]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[23]  L. Rabiner,et al.  Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and Narrow-Band Filtering , 1975 .

[24]  Xiong Liu A High Speed Digital Decimation Filter with Parallel Cascaded Integrator-Comb Pre-Filters , 2009, 2009 2nd International Congress on Image and Signal Processing.

[25]  Rocío del Río,et al.  CMOS Sigma-Delta Converters: Practical Design Guide , 2013 .

[26]  Alan N. Willson,et al.  Application of filter sharpening to cascaded integrator-comb decimation filters , 1997, IEEE Trans. Signal Process..

[27]  Gordana Jovanovic Dolecek,et al.  Zero-rotation-based nonrecursive comb structure , 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

[28]  R. W. Stewart An overview of sigma delta ADCs and DAC devices , 1995 .

[29]  S. Park,et al.  Multi-stage IIR decimation filter design technique for high resolution sigma-delta A/D converters , 1992, [1992] Conference Record IEEE Instrumentation and Measurement Technology Conference.

[30]  Lirida A. B. Naviner,et al.  On design and implementation of a decimation filter for multistandard wireless transceivers , 2002, IEEE Trans. Wirel. Commun..

[31]  Massimiliano Laddomada,et al.  An improved class of multiplierless decimation filters: Analysis and design , 2013, Digit. Signal Process..

[32]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[33]  M. Laddomada Generalized Comb Decimation Filters for $\Sigma\Delta$ A/D Converters: Analysis and Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[34]  Jing Li,et al.  VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application , 2011, 2011 9th IEEE International Conference on ASIC.

[35]  Truong Q. Nguyen,et al.  A 'trick' for the design of FIR half-band filters , 1987 .

[36]  Vishal Saxena,et al.  Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs , 2011, 2011 IEEE International SOC Conference.

[37]  Amin Nassar,et al.  Power-Efficient Clock/Data Distribution Technique for Polyphase Comb Filter in Digital Receivers , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[38]  Guillermo A. Jaquenod,et al.  Digital Signal Processing, A Computer Based Approach . 2nd Edition , 2003 .

[39]  José Manuel de la Rosa,et al.  Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[40]  Seongdo Kim,et al.  Design of CIC roll-off compensation filter in a W-CDMA digital IF receiver , 2006, Digit. Signal Process..

[41]  G. Jovanovic Dolecek Simple wideband CIC compensator , 2009 .

[42]  Letizia Lo Presti,et al.  Efficient modified-sinc filters for sigma-delta A/D converters , 2000 .

[43]  Bruce A. Wooley,et al.  A low-power, area-efficient digital filter for decimation and interpolation , 1994, IEEE J. Solid State Circuits.

[44]  Mladen Vucic,et al.  Closed-Form Design of CIC Compensators Based on Maximally Flat Error Criterion , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[45]  Rozita Teymourzadeh,et al.  VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications , 2006 .

[46]  Shing-Chow Chan,et al.  The design and multiplier-less realization of software radio receivers with reduced system delay , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[47]  Gordana Jovanovic Dolecek,et al.  Trigonometrical approach to design a simple wideband comb compensator , 2014 .

[48]  R.K. James,et al.  Polyphase Implementation of Non-recursive Comb Decimators for Sigma-Delta A/D Converters , 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.

[49]  Wolfgang H. Krautschneider,et al.  Comparison of Decimation Filter Architectures for a Sigma-Delta Analog to Digital Converter , 2010 .

[50]  Nagendra Krishnapura,et al.  A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[51]  Stephen A. Dyer,et al.  Digital signal processing , 2018, 8th International Multitopic Conference, 2004. Proceedings of INMIC 2004..

[52]  Brad Brannon Understanding state of the art in ADCs , 2008 .