Exploiting idle cycles for algorithm level re-computing

Deep sub-micron VLSI circuits are susceptible to permanent and transient faults. Several techniques for concurrent error detection (CED) recovery and correction have been proposed to target permanent and transient faults. We propose a new register transfer (RT) level time redundancy based CED technique that exploits the idle cycles in the data path. Although algorithm level re-computing techniques can trade-off the detection capability of CED vs. time overhead, it results in 100 % time overhead when the strongest CED capability is achieved.. Using the idle cycles in the data path to do the re-computation can reduce this time overhead. However dependencies between operations prevent the recomputation from fully utilizing the idle cycles. Deliberately breaking some of these data dependencies can further reduce the time overhead associated with algorithm level re-computing.

[1]  Vincenzo Piuri,et al.  Optimising high-level synthesis for self-checking arithmetic circuits , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[2]  Alex Orailoglu,et al.  Transient and intermittent fault recovery without rollback , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[3]  Alex Orailoglu,et al.  High-level synthesis of gracefully degradable ASICs , 1996, Proceedings ED&TC European Design and Test Conference.

[4]  Ramesh Karri,et al.  Algorithm level re-computing-a register transfer level concurrent error detection technique , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[5]  Alex Orailoglu,et al.  Microarchitectural synthesis of ICs with embedded concurrent fault isolation , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[6]  Ramesh Karri,et al.  Phantom redundancy: a high-level synthesis approach for manufacturability , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[7]  Miodrag Potkonjak,et al.  High level synthesis techniques for efficient built-in-self-repair , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[8]  A. Orailoglu.  Graceful degradation in synthesis of VLSI ICs , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[9]  Vincenzo Piuri,et al.  Semi-concurrent error detection in data paths , 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[10]  Ramesh Karri,et al.  Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors , 1996, IEEE Trans. Reliab..

[11]  S. S. Ravi,et al.  Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths , 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

[12]  Vincenzo Piuri,et al.  High-level synthesis of data paths with concurrent error detection , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[13]  A. Orailoglu,et al.  Scheduling with rollback constraints in high-level synthesis of self-recovering ASICs , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

[14]  Fadi J. Kurdahi,et al.  Optimal algorithms for recovery point insertion in recoverable microarchitectures , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Ramesh Karri,et al.  Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs , 2001, TODE.

[16]  Niraj K. Jha,et al.  Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.