configuration detection circuit.

The present invention relates to a pattern detection circuit used by a parallel processing system wherein high speed data string is divided into multiple parallel data so that these multiple parallel data are processed at a low speed. The pattern detection circuit detects a frame detection pattern representing a positional relationship between the multiple parallel data. The multiple parallel data input is delayed by one clock period; and then a first comparison circuit compares the received parallel data with the delayed parallel data to detect an initial portion of the frame detection pattern. Then, the multiple parallel delayed data are sorted according to an order defined by the detected frame detection pattern. A second comparison circuit compares the multiple parallel data sorted therebetween for detecting a remaining portion of the frame detection pattern. A detection signal corresponding to the detection of the frame detection pattern is further produced based on the outputs of the comparison circuits. Each of these comparison circuits consists of exclusive-OR circuits whose number is relatively small.