Physical design algorithms for asynchronous circuits
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[1] Chung-Kuan Cheng,et al. Prime: A Timing-Driven Placement Tool Using A Piecewise Linear Resistive Network Approach , 1993, 30th ACM/IEEE Design Automation Conference.
[2] Jochen A. G. Jess,et al. Gate sizing in MOS digital circuits with linear programming , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[3] John P. Fishburn,et al. Clock Skew Optimization , 1990, IEEE Trans. Computers.
[4] Jun-Dong Cho,et al. Ultra-high density standard cell library using multi-height cell structure , 2008, Micro + Nano Materials, Devices, and Applications.
[5] Ran Ginosar,et al. Relative timing , 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[6] Peter A. Beerel,et al. Slack matching asynchronous designs , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).
[7] Peter A. Beerel,et al. A Designer's Guide to Asynchronous VLSI , 2010 .
[8] Guilherme Flach,et al. Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Jack Edmonds,et al. Maximum matching and a polyhedron with 0,1-vertices , 1965 .
[10] David G. Chinnery,et al. Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization , 2003, ISLPED '03.
[11] Ali Dasdan,et al. Experimental analysis of the fastest optimum cycle ratio and mean algorithms , 2004, TODE.
[12] Alexandre Yakovlev,et al. Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[13] Dongjin Lee,et al. SimPL: An effective placement algorithm , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[14] Kwang-Ting Cheng,et al. Electronic Design Automation: Synthesis, Verification, and Test , 2009 .
[15] Piyush Prakash,et al. Slack matching quasi delay-insensitive circuits , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).
[16] Igor L. Markov,et al. Combinatorial techniques for mixed-size placement , 2005, TODE.
[17] Mallika Prakash. LIBRARY CHARACTERIZATION AND STATIC TIMING ANALYSIS OF ASYNCHRONOUS CIRCUITS , 2007 .
[18] Steven M. Burns,et al. An improved benchmark suite for the ISPD-2013 discrete cell sizing contest , 2013, ISPD '13.
[19] Chris C. N. Chu,et al. Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[20] Gi-Joon Nam,et al. The ISPD2005 placement contest and benchmark suite , 2005, ISPD '05.
[21] Peter A. Beerel,et al. Proteus: An ASIC Flow for GHz Asynchronous Designs , 2011, IEEE Design & Test of Computers.
[22] Natarajan Viswanathan,et al. ICCAD-2013 CAD contest in placement finishing and benchmark suite , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[23] Jan Magott,et al. Performance Evaluation of Concurrent Systems Using Petri Nets , 1984, Inf. Process. Lett..
[24] Kamal Chaudhary,et al. RITUAL: a performance driven placement algorithm , 1992 .
[25] Sung-Mo Kang,et al. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[26] Jan Tijmen Udding,et al. A formal model for defining and classifying delay-insensitive circuits and systems , 1986, Distributed Computing.
[27] Chris C. N. Chu,et al. FastPlace: an analytical placer for mixed-mode designs , 2005, ISPD '05.
[28] Robert E. Tarjan,et al. 7. Shortest Paths , 1983 .
[29] Guilherme Flach,et al. Jezz: An effective legalization algorithm for minimum displacement , 2015, 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI).
[30] Seth Pettie,et al. Linear-Time Approximation for Maximum Weight Matching , 2014, JACM.
[31] Peter A. Beerel,et al. Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.
[32] Robert E. Tarjan,et al. Faster parametric shortest path and minimum-balance algorithms , 1991, Networks.
[33] Ismail Bustany,et al. POLAR: Placement based on novel rough legalization and refinement , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[34] Christos P. Sotiriou,et al. CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits , 2011, 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems.
[35] Ali Dasdan,et al. An Experimental Study of Minimum Mean Cycle Algorithms , 1998 .
[36] Peter A. Beerel,et al. A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design , 2014, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems.
[37] Ivan E. Sutherland,et al. GasP: a minimal FIFO control , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.
[38] Andrew M Lines,et al. Pipelined Asynchronous Circuits , 1998 .
[39] Ernest S. Kuh,et al. An Algorithm for Performance-Driven Placement of Cell-Based ICs , 1991 .
[40] Richard M. Karp,et al. Parametric shortest path algorithms with an application to cyclic staffing , 1981, Discret. Appl. Math..
[41] K. J. Ray Liu,et al. Adaptive negative cycle detection in dynamic graphs , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[42] Peter A. Beerel,et al. Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits , 2014, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems.
[43] Stephen Longfield,et al. Timing Driven Placement for Quasi Delay-Insensitive Circuits , 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.
[44] Chris C. N. Chu,et al. Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[45] Andrew V. Goldberg,et al. Shortest paths algorithms: Theory and experimental evaluation , 1994, SODA '94.
[46] Edmund Y. Lam,et al. Standard Cell Layout With Regular Contact Placement , 2004 .
[47] Chris C. N. Chu,et al. An efficient and effective detailed placement algorithm , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[48] Michael Burstein,et al. Timing Influenced Layout Design , 1985, 22nd ACM/IEEE Design Automation Conference.
[49] Frank M. Johannes,et al. Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[50] Charlie Chung-Ping Chen,et al. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, ICCAD.
[51] Steven M. Burns,et al. The ISPD-2012 discrete cell sizing contest and benchmark suite , 2012, ISPD '12.
[52] Hai Zhou,et al. Gate sizing by Lagrangian relaxation revisited , 2007, ICCAD 2007.
[53] Tao Lin,et al. Asynchronous circuit placement by Lagrangian relaxation , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[54] Andrew B. Kahng,et al. Mixed cell-height implementation for improved design quality in advanced nodes , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[55] Jin Hu,et al. Sensitivity-guided metaheuristics for accurate discrete gate sizing , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[56] Hossein Pedram,et al. Low power asynchronous circuit back-end design flow , 2011, Microelectron. J..
[57] Jason Cong,et al. A robust detailed placement for mixed-size IC designs , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[58] Charles E. Leiserson,et al. Optimizing synchronous systems , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).
[59] John P. Fishburn,et al. TILOS: A posynomial programming approach to transistor sizing , 2003, ICCAD 2003.
[60] Georg Sigl,et al. GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[61] Edith Beigné,et al. A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.
[62] L.P.P.P. van Ginneken,et al. Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990, IEEE International Symposium on Circuits and Systems.
[63] Seth Copen Goldstein,et al. Leveraging protocol knowledge in slack matching , 2006, ICCAD.
[64] Yih-Lang Li,et al. Density-aware detailed placement with instant legalization , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[65] Wing Ning. Strongly NP-hard discrete gate-sizing problems , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[66] Kiyoshi Oguri,et al. Asynchronous Circuit Design , 2001 .
[67] Mokhtar S. Bazaraa,et al. Nonlinear Programming: Theory and Algorithms , 1993 .
[68] Chris C. N. Chu,et al. Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation , 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.
[69] Hiroshi Saito,et al. A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation , 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).
[70] James Lyle Peterson,et al. Petri net theory and the modeling of systems , 1981 .
[71] C. Reeves. Modern heuristic techniques for combinatorial problems , 1993 .
[72] Stefan Hougardy,et al. A simple approximation algorithm for the weighted matching problem , 2003, Inf. Process. Lett..
[73] Steven M. Burns,et al. Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[74] Marcelo de Oliveira Johann,et al. Fast and efficient Lagrangian Relaxation-based Discrete Gate Sizing , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[75] Pravin M. Vaidya,et al. A performance driven macro-cell placement algorithm , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[76] R. Bellman,et al. Dynamic Programming and Markov Processes , 1960 .
[77] Andreas Kuehlmann,et al. Physical placement driven by sequential timing analysis , 2004, ICCAD 2004.
[78] Steven M. Nowick,et al. MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[79] Paul I. Pénzes,et al. The design of an asynchronous MIPS R3000 microprocessor , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.