论文信息 - LBW COST SCEEMES FOR FAULT TOLEEANCE IN MATRIX OPERATIONS WITH PROCESSOR ARRAYS - 字舞流文

LBW COST SCEEMES FOR FAULT TOLEEANCE IN MATRIX OPERATIONS WITH PROCESSOR ARRAYS

Jacob A. Abraham | Knang-Ena K. Eoang | J. Abraham

[1] Janak H. Patel,et al. Concurrent Error Detection in ALU's by Recomputing with Shifted Operands , 1982, IEEE Transactions on Computers.

[2] D. F. Barbe,et al. VHSIC Systems and Technology , 1981, Computer.

[3] Yves Crouzet,et al. Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor , 1980, IEEE Transactions on Computers.

[4] John J. Shedletsky,et al. Error Correction by Alternate-Data Retry , 1978, IEEE Transactions on Computers.

[5] Richard W. Hamming,et al. Error detecting and error correcting codes , 1950 .

[6] D. A. Anderson,et al. Design of self-checking digital networks using coding techniques , 1971 .

[7] J. von Neumann,et al. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .