Comparative energy and delay of energy recovery and square wave clock flip-flops for high-performance and low-power applications

Flip-flops are essential elements of a design from both delay and energy aspects. A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes are promising approaches for future designs. Recently, there has been published several energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. However, there has not been shown any extensive power and delay comparison between energy-recovery and square clock flip-flops. We compare the energy recovery flip-flops with square wave clock flip-flops in terms of power, delay, and area. Based on the simulation results using BPTM 0.18 /spl mu/m CMOS technology, at a frequency of 200 MHz, the differential energy recovery flip-flops exhibit more than 14% delay reduction and power reduction of more than 43% compared to the differential square-wave clock flip-flops. The single-ended energy recovery flip-flops show more than 22% delay reduction and power reduction of more than 16% compared to the single-ended square wave clock flip-flops.