A 800MS/s, 150µV input-referred offset single-stage latched comparator

In the proposed single-stage comparator, the comparison cycle is divided into six phases to cancel the static offset and then perform comparison. Operations, except in reset, are scheduled by applying small voltage variations, up to 200mVolts, on bulk terminals of concurrently used negative and positive feedback PMOS devices. Negative feedback restricts the gain of the main comparison and the offset cancellation loop during pre-amplification. Pre-amplification phase is intentionally added before the latch operation to remove the concerns of the erroneous latch of unpredictable residues which might be remained across the reset switch from the last comparison. The negative and positive feedback devices also impart in offset cancellation loop to provide high loop gain and remove the need for auxiliary amplifier. Worst-Case simulation results confirms that the proposed comparator can detect 1.5mVolts input difference, at all process corners, in presence of 15mVolts input offset voltage, at 800MS/s comparison rate. The Monte-Carlo analysis for 100 iterations on input offset voltages shows that input referred offset would be improved to 150μV while was 6mVolts at 1σ before correction. Power consumption is 0.78mW at 800MS/s comparison speed. Simulations are performed using the BSIM3 model of a 0.18μm CMOS technology.