A Noise-Efficient 36 nV/ $\surd $ Hz Chopper Amplifier Using an Inverter-Based 0.2-V Supply Input Stage

This paper presents an analog front end (AFE) that achieves a high noise efficiency by using a chopper amplifier with a 0.2-V supply inverter-based input stage followed by a 0.8-V supply stage. The high input-stage current needed to reduce the input-referred noise is drawn from the 0.2-V supply, significantly reducing power consumption. The 0.8 V stage provides high gain and signal swing, improving linearity. Biasing and common-mode rejection techniques for the ultra-low-voltage stage are presented. The AFE is implemented in a 0.18 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process and integrates the chopper low-noise instrumentation amplifier, a programmable-gain amplifier, and an antialiasing filter. The AFE consumes 0.79 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> and achieves a competitive power efficiency factor (PEF) of 1.6 and an input noise of 0.94 <inline-formula> <tex-math notation="LaTeX">$\mu \text{V}_{\text {rms}}$ </tex-math></inline-formula> integrated from 0.5 to 670 Hz while maintaining a 36 nV/<inline-formula> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula>Hz input noise density down to 0.5 Hz. The included 0.8/0.2-V buck converter may be used to provide the 0.2-V supply at 72%–74% efficiency without significantly increasing noise, yielding a PEF of 1.8.

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