Formal Verification of ECCs for Memories Using ACL2

Due to the ever-increasing toll of soft errors in memories, Error Correction Codes (ECCs) like Hamming and Reed-Solomon Codes have been used to protect data in memories, in applications ranging from space to terresterial work stations. In past seven decades, most of the research has focused on providing better ECC strategies for data integrity in memories, but the same pace research efforts have not been made to develop better verification methodologies for the newer ECCs. As the memory sizes keep increasing, exhaustive simulation-based testing of ECCs is no longer practical. Hence, formal verification, particularly theorem proving, provides an efficient, yet scarcely explored, alternative for ECC verification. We propose a framework, with extensible libraries, for the formal verification of ECCs using the ACL2 theorem prover. The framework is easy to use and particularly targets the needs of formally verified ECCs in memories. We also demonstrate the usefulness of the proposed framework by verifying two of the most commonly used ECCs, i.e., Hamming and Convolutional codes. To illustrate that the ECCs verified using our formal framework are practically reliable, we utilized a formal record-based memory model to formally verify that the inherent properties of the ECCs like hamming distance, codeword decoding, and error detection/correction remain consistent even when the ECC is implemented on the memory.

[1]  Rached Tourki,et al.  A deep analysis of SEU consequences in the internal memory of LEON3 processor , 2016, 2016 17th Latin-American Test Symposium (LATS).

[2]  Edmund M. Clarke,et al.  Formal Methods: State of the Art and Future Directions Working Group Members , 1996 .

[3]  Pedro Reviriego,et al.  Matrix-Based Codes for Adjacent Error Correction , 2010, IEEE Transactions on Nuclear Science.

[4]  Pascal Fradet,et al.  Verification-guided voter minimization in triple-modular redundant circuits , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[6]  Elisabeth de Carvalho,et al.  Hybrid Forwarding Scheme for Cooperative Relaying in OFDM Based Networks , 2006, 2006 IEEE International Conference on Communications.

[7]  Emmanuelle Encrenaz-Tiphène,et al.  Feasibility analysis for robustness quantification by symbolic model checking , 2011, Formal Methods Syst. Des..

[8]  Manabu Hagiwara,et al.  Formalization of coding theory using lean , 2016, 2016 International Symposium on Information Theory and Its Applications (ISITA).

[9]  C.W. Slayman,et al.  Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations , 2005, IEEE Transactions on Device and Materials Reliability.

[10]  D. Binder,et al.  Satellite Anomalies from Galactic Cosmic Rays , 1975, IEEE Transactions on Nuclear Science.

[11]  Pedro Reviriego,et al.  Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Régis Leveugle,et al.  A new approach for early dependability evaluation based on formal property checking and controlled mutations , 2005, 11th IEEE International On-Line Testing Symposium.

[13]  Jie-Hong Roland Jiang,et al.  To SAT or Not to SAT: Scalable Exploration of Functional Dependency , 2010, IEEE Transactions on Computers.

[14]  Edmund M. Clarke,et al.  Model Checking , 1999, Handbook of Automated Reasoning.

[15]  Beate Bollig,et al.  Improving the Variable Ordering of OBDDs Is NP-Complete , 1996, IEEE Trans. Computers.

[16]  Wenchao Li,et al.  Verification-guided soft error resilience , 2007 .

[17]  Sandip Ray,et al.  Integrating external deduction tools with ACL2 , 2006, J. Appl. Log..

[18]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[19]  Jacques Garrigue,et al.  Formalization of Reed-Solomon codes and progress report on formalization of LDPC codes , 2016, 2016 International Symposium on Information Theory and Its Applications (ISITA).

[20]  Christopher Preschern,et al.  Formal Fault Tolerance Analysis of Algorithms for Redundant Systems in Early Design Stages , 2014, SERENE.

[21]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[22]  Prabhakar Kudva,et al.  Automated detection and verification of parity-protected memory elements , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[23]  Pedro Reviriego,et al.  Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes Through Selective Shortening and Bit Placement , 2014, IEEE Transactions on Device and Materials Reliability.

[24]  Robert S. Boyer,et al.  Functional Instantiation in First-Order Logic , 1991, Artificial and Mathematical Theory of Computation.

[25]  Stefan Frehse,et al.  Effective Robustness Analysis Using Bounded Model Checking Techniques , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Lawrence C. Paulson,et al.  A Pragmatic Approach to Extending Provers by Computer Algebra - with Applications to Coding Theory , 1999, Fundam. Informaticae.

[27]  James L. Walsh,et al.  IBM experiments in soft fails in computer electronics (1978-1994) , 1996, IBM J. Res. Dev..

[28]  Luigi Carro,et al.  Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults , 2000, J. Electron. Test..

[29]  Panagiotis Manolios,et al.  Computer-Aided Reasoning: An Approach , 2011 .

[30]  Nur A. Touba,et al.  Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Andrew J. Viterbi,et al.  Convolutional Codes and Their Performance in Communication Systems , 1971 .

[32]  Jared Davis.  Memories: array-like records for ACL2 , 2006, ACL2 '06.

[33]  P. Reviriego,et al.  Enhanced Detection of Double and Triple Adjacent Errors in Hamming Codes Through Selective Bit Placement , 2012, IEEE Transactions on Device and Materials Reliability.

[34]  T. May,et al.  Alpha-particle-induced soft errors in dynamic memories , 1979, IEEE Transactions on Electron Devices.

[35]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[36]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[37]  Jacques Garrigue,et al.  Formalization of Error-Correcting Codes: From Hamming to Modern Coding Theory , 2015, ITP.

[38]  Jacques Garrigue,et al.  A Library for Formalization of Linear Error-Correcting Codes , 2020, Journal of Automated Reasoning.

[39]  Fabio Salice,et al.  Convolutional Coding for SEU mitigation , 2008, 2008 13th European Test Symposium.

[40]  Luis Alfonso Lastras-Montaño,et al.  Formal verification of error correcting circuits using computational algebraic geometry , 2012, 2012 Formal Methods in Computer-Aided Design (FMCAD).

[41]  Heinrich Theodor Vierhaus,et al.  Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[42]  Dhiraj K. Pradhan,et al.  Matrix Codes for Reliable and Cost Efficient Memory Chips , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[43]  Gianpiero Cabodi,et al.  BDD-Based Hardware Verification , 2006, SFM.

[44]  Aabhas Rastogi,et al.  SEU MITIGATION-using 1/3 rate convolution coding , 2009, 2009 2nd IEEE International Conference on Computer Science and Information Technology.

[45]  Nur A. Touba,et al.  Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs , 2018, ACM Great Lakes Symposium on VLSI.

[46]  Bixin Li,et al.  A classification and comparison of model checking software architecture techniques , 2010, J. Syst. Softw..

[47]  Stefan Frehse,et al.  Robustness Check for Multiple Faults Using Formal Techniques , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[48]  Laurence Pierre,et al.  ACL2 for the verification of fault-tolerance properties: first results , 2009, ACL2 '09.

[49]  David J. Webb,et al.  Formalization of Insertion/Deletion Codes and the Levenshtein Metric in Lean , 2018, 2018 International Symposium on Information Theory and Its Applications (ISITA).

[50]  L. Carro,et al.  Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy , 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.