Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests

This paper describes a new approach to static test compaction for scan circuits that modifies tests in order to reduce the number of tests in a test set. The main contribution of this paper is a procedure referred to as restoration. In a basic step, the restoration procedure considers two tests, t<sub>rem</sub> and t<sub>mod</sub>, with sets of detected faults D<sub>rem</sub> and D<sub>mod</sub>, respectively. Starting from t<sub>new</sub> = t<sub>mod</sub>, and considering t<sub>new</sub> as a variation of t<sub>rem</sub>, the procedure restores bits of t<sub>rem</sub> into t<sub>new</sub> as necessary to ensure that faults from D<sub>rem</sub> are detected by t<sub>new</sub>. The procedure then restores bits of t<sub>mod</sub> into t<sub>new</sub> as necessary to ensure that all the faults from D<sub>mod</sub> are detected by t<sub>new</sub>. The test t<sub>new</sub> is used for replacing t<sub>mod</sub>, and the faults it detects out of D<sub>rem</sub> are moved to D<sub>mod</sub>. After several such steps, if Drem becomes empty, t<sub>rem</sub> can be removed from the test set. The procedure is applied to test sets that are already compacted. The results show that the procedure can achieve significant additional compaction even without considering all the tests for removal or modification.

[1]  Irith Pomeranz,et al.  Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[2]  Irith Pomeranz.  On Test Compaction of Broadside and Skewed-Load Test Cubes , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Kuen-Jong Lee,et al.  Using a single input to support multiple scan chains , 1998, ICCAD '98.

[4]  Aiman H. El-Maleh,et al.  Test vector decomposition-based static compaction algorithms for combinational circuits , 2003, TODE.

[5]  Irith Pomeranz,et al.  Forward-looking fault simulation for improved static compaction , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[7]  Nur A. Touba,et al.  Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.

[8]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[9]  Paulo F. Flores,et al.  On applying set covering models to test set compaction , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[10]  Tsuneo Nakata,et al.  A method of static compaction of test stimuli , 2001, Proceedings 10th Asian Test Symposium.

[11]  Irith Pomeranz,et al.  Static test compaction for delay fault test sets consisting of broadside and skewed-load tests , 2011, 29th VLSI Test Symposium.

[12]  Irith Pomeranz,et al.  ROTCO: a reverse order test compaction technique , 1992, Proceedings Euro ASIC '92.

[13]  Irith Pomeranz,et al.  On static test compaction and test pattern ordering for scan designs , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[14]  Irith Pomeranz,et al.  Vector restoration based static compaction of test sequences for synchronous sequential circuits , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[15]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[16]  Dorit S. Hochbaum,et al.  An optimal test compression procedure for combinational circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..