Can concurrent checkers help BIST?

Concurrent checkers are commonly used in computer systems to detect computational errors on-line, which enhances reliability. Using the coding theory framework developed earlier by the authors, concurrent checkers already available within the circuit are shown to be significant help to off-line testing. Specifically, test time can be reduced while improving the fault escape probability. The proposed combined scheme can be implemented with simple modification of existing hardware. Specifically proposed is a novel, dual use of concurrent checkers and BIST hardware, yielding mutual advantage.

[1]  Dhiraj K. Pradhan,et al.  A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression , 1991, IEEE Trans. Computers.

[2]  Kazuhiko Iwasaki,et al.  Design of signature circuits based on weight distributions of error-correcting codes , 1990, Proceedings. International Test Conference 1990.

[3]  Eiji Fujiwara,et al.  A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing , 1987, IEEE Transactions on Computers.

[4]  André Ivanov,et al.  An iterative technique for calculating aliasing probability of linear feedback signature registers , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[5]  Dhiraj K. Pradhan,et al.  A new framework for designing and analyzing BIST techniques: computation of exact aliasing probability , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[6]  Nirmal R. Saxena,et al.  Simultaneous signature and syndrome compression , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Yervant Zorian,et al.  EEODM: An effective BIST scheme for ROMs , 1990, Proceedings. International Test Conference 1990.

[8]  Dhiraj K. Pradhan,et al.  Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model , 1991, 1991, Proceedings. International Test Conference.

[9]  Dhiraj K. Pradhan,et al.  Aliasing Probability for Multiple Input Signature Analyzer , 1990, IEEE Trans. Computers.

[10]  K. Iwasaki,et al.  An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  F. MacWilliams,et al.  The Theory of Error-Correcting Codes , 1977 .

[12]  Edward J. McCluskey,et al.  Concurrent Error Detection and Testing for Large PLA's , 1982 .

[13]  Michael Nicolaidis A unified built-in-test scheme: UBIST , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[14]  W. Daehn,et al.  Aliasing errors in multiple input signature analysis registers , 1989, [1989] Proceedings of the 1st European Test Conference.

[15]  K. Iwasaki Analysis and proposal of signature circuits for LSI testing , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Ian F. Blake,et al.  On the Complete Weight Enumerator of Reed-Solomon Codes , 1991, SIAM J. Discret. Math..

[17]  B. Ricco,et al.  Aliasing in signature analysis testing with multiple-input shift-registers , 1989, [1989] Proceedings of the 1st European Test Conference.

[18]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .