A new case for the TAGE branch predictor

The TAGE predictor is often considered as state-of-the-art in conditional branch predictors proposed by academy. In this paper, we first present directions to reduce the hardware implementation cost of TAGE. Second we show how to further reduce the misprediction rate of TAGE through augmenting it with small side predictors.

[1]  Joseph T. Rahmeh,et al.  Improving the accuracy of dynamic branch prediction using branch correlation , 1992, ASPLOS V.

[2]  Andreas Moshovos,et al.  SEPAS: A highly accurate energy-efficient branch predictor , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[3]  André Seznec,et al.  The L-TAGE Branch Predictor , 2007, J. Instr. Level Parallelism.

[4]  Yale N. Patt,et al.  A two-level approach to making class predictions , 2003, 36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the.

[5]  Daniel A. Jiménez,et al.  Fast Path-Based Neural Branch Prediction , 2003, MICRO.

[6]  Norman P. Jouppi,et al.  CACTI 6.0: A Tool to Model Large Caches , 2009 .

[7]  Daniel A. Jiménez,et al.  Low-power, high-performance analog neural branch prediction , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[8]  André Seznec.  Analysis of the O-GEometric History Length Branch Predictor , 2005, ISCA 2005.

[9]  Trevor N. Mudge,et al.  The YAGS branch prediction scheme , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[10]  S. McFarling.  Combining Branch Predictors , 1993 .

[11]  Daniel A. Jiménez,et al.  Piecewise linear branch prediction , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[12]  Pierre Michaud,et al.  A PPM-like, Tag-based Predictor. , 2005 .

[13]  Yale N. Patt,et al.  The agree predictor: a mechanism for reducing negative branch history interference , 1997, ISCA '97.

[14]  André Seznec.  A 64 Kbytes ISL-TAGE branch predictor , 2011 .

[15]  Yasuo Ishii.  Fused Two-Level Branch Prediction with Ahead Calculation , 2007, J. Instr. Level Parallelism.

[16]  Yiannakis Sazeides,et al.  Design tradeoffs for the Alpha EV8 conditional branch predictor , 2002, ISCA.

[17]  André Seznec.  Storage free confidence estimation for the TAGE branch predictor , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[18]  Yi Ma,et al.  Address-branch correlation: A novel locality for long-latency hard-to-predict branches , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[19]  Y.N. Patt,et al.  Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches , 1996, 23rd Annual International Symposium on Computer Architecture (ISCA'96).

[20]  Pierre Michaud,et al.  A case for (partially) TAgged GEometric history length branch prediction , 2006, J. Instr. Level Parallelism.

[21]  Daniel A. Jiménez,et al.  The impact of delay on the design of branch predictors , 2000, MICRO 33.

[22]  Huiyang Zhou,et al.  Adaptive Information Processing: An Effective Way to Improve Perceptron Predictors , 2005, J. Instr. Level Parallelism.

[23]  Daniel A. Jiménez,et al.  Reconsidering complex branch predictors , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[24]  A. Seznec,et al.  Trading Conflict And Capacity Aliasing In Conditional Branch Predictors , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[25]  Dana S. Henry,et al.  Predicting conditional branches with fusion-based hybrid predictors , 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

[26]  Daniel A. Jiménez.  OH-SNAP : Optimized Hybrid Scaled Neural Analog Predictor , 2011 .

[27]  Daniel A. Jiménez,et al.  Dynamic branch prediction with perceptrons , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.