Comparative study of meta-heuristic 3D floorplanning algorithms

Constant necessity of improving performance has brought the invention of 3D chips. The improvement is achieved due to the reduction of wire length, which results in decreased interconnection delay. However, 3D stacks have less heat dissipation due to the inner layers, which leads to increased temperature and the appearance of hot spots. This problem can be mitigated through appropriate floorplanning. For this reason, in this work we present and compare five different solutions for floorplanning of 3D chips. Each solution uses a different representation, and all are based on meta-heuristic algorithms, namely three of them are based on simulated annealing, while two other are based on evolutionary algorithms. The results show great capability of all the solutions in optimizing temperature and wire length, as they all exhibit significant improvements comparing to the benchmark floorplans. HighlightsComparison of five floorplanning solutions for 3D chips in terms of temperature and wirelength.We employ heuristics and evolutionary algorithms; all have been extensively tested.Solutions obtained exhibit great improvements compared with the original 3D chip floorplan.We finally explore the multi-objective problem, considering heat dissipation and wire length.Both single and multi objective are non dominated in different regions of the Pareto front.