Limitations of the VCO-Based Quantizer

In the following sections, both quantizers are compared in the presence of circuit nonidealities such as VCO nonlinearity, phase noise, and sampling clock jitter. These nonidealities are added to the VerilogA model, and theoretical equations are derived to verify the effects on each quantizer. Although the FDC has been widely adopted due to its inherent first-order noise shaping characteristic, the noise shaping is shown to degrade in the presence of phase noise and clock jitter. Other circuit nonidealities exist but are ignored in this analysis since these quantizers are highly digital circuits.

[1]  R. Farjad-Rad,et al.  A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  Kenneth S. Kundert,et al.  VCO jitter simulation and its comparison with measurement , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[3]  Jaewook Kim,et al.  Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Rick Poore,et al.  Phase Noise and Jitter , 2001 .