A Novel Ant Colony Optimization Based Temperature-Aware Floorplanning Algorithm

In this paper, an ant colony optimization based temperature-aware floorplanning algorithm is proposed. The object of temperature-aware floorplanning is to decrease the temperature gradient and the area occupancy simultaneously. First, the problem is presented based on Ant Colony Optimization (ACO). Then, with multi-objective optimization, two methods are adopted for decreasing the temperature difference and the area occupancy for the first time for MCNC benchmark Circuits. Simulation Results show that the DeltaTmax can be at most optimized to 7.8degC or 14.6deg C when the DeltaTmax for initial floorplan is 27.4deg C, while the best area occupancy is 87.9% or 89.7%. Compared to Simulated Annealing (SA) algorithm, our results show great improvement in speed with little area latency.

[1]  Srinivas Katkoori,et al.  Ant colony system application to macrocell overlap removal , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Thomas Stützle,et al.  Ant colony optimization: artificial ants as a computational intelligence technique , 2006 .

[3]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[4]  Thomas Stützle,et al.  MAX-MIN Ant System , 2000, Future Gener. Comput. Syst..

[5]  Nobuto Ono,et al.  On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design , 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[6]  Sung-Mo Kang,et al.  Cell-level placement for improving substrate thermal distribution , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Takeshi Yoshimura,et al.  Floorplanning using a tree representation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Yao-Wen Chang,et al.  B*-trees: a new representation for non-slicing floorplans , 2000, Proceedings 37th Design Automation Conference.

[9]  Kevin Skadron,et al.  Monitoring temperature in FPGA based SoCs , 2005, 2005 International Conference on Computer Design.

[10]  H. Teng,et al.  An ant colony optimization based layout optimization algorithm , 2002, 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings..

[11]  R. J. Mack,et al.  VLSI physical design automation: theory and practice , 1996 .

[12]  Ning Xu,et al.  A Fast Algorithm for VLSI Building Block Placement , 2006, The Proceedings of the Multiconference on "Computational Engineering in Systems Applications".

[13]  Robert W. Dutton,et al.  Full chip thermal simulation , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

[14]  Kevin Skadron,et al.  Temperature-Aware Computer Systems: Opportunities and Challenges , 2003, IEEE Micro.

[15]  Marco Dorigo,et al.  Optimization, Learning and Natural Algorithms , 1992 .