A 100 MHz-1GHz on-chip-programmable phase-locked loop

A programmable wide-range PLL has been designed in the digital subset of TSMC 3.3V, 0.25/spl mu/ technology that can provide 100-MHz to 1-GHz rail-to-rail digital clock signal from a 50-MHz reference clock. The architecture is appropriate for low-power design. The system is robust against temperature changes so that the stability of the system is guaranteed. Because of the differential configuration of the sub-blocks and using a voltage-controlled oscillator with a low gain and a linear transfer function the system has an acceptable noise rejection.

[1]  B. Razavi.  Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .

[2]  Suki Kim,et al.  A wide range PLL for 64X speed CD-ROMs & 10X speed DVD-ROMs , 2000, IEEE Trans. Consumer Electron..

[3]  Alan B. Grebene,et al.  Analog Integrated Circuit Design , 1978 .

[4]  M. Horowitz,et al.  Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[5]  Oscal T.-C. Chen,et al.  A power-efficient wide-range phase-locked loop , 2002, IEEE J. Solid State Circuits.

[6]  V. von Kaenel,et al.  A 4-GHz clock system for a high-performance system-on-a-chip design , 2001 .

[7]  Zeljko Zilic,et al.  A new PLL design for clock management applications , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).