Efficient Path Delay Test Generation for Custom Designs

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

[1]  Kurt Keutzer,et al.  A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits , 1991, 1991, Proceedings. International Test Conference.

[2]  Kurt Keutzer,et al.  Delay-fault test generation and synthesis for testability under a standard scan design methodology , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Irith Pomeranz,et al.  Functional test generation for delay faults in combinational circuits , 1995, TODE.

[5]  Michael H. Schulz,et al.  Parallel Pattern Fault Simulation of Path Delay Faults , 1989, 26th ACM/IEEE Design Automation Conference.

[6]  Kurt Keutzer,et al.  Robust delay-fault test generation and synthesis for testability under a standard scan design methodology , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  Spyros Tragoudas,et al.  Functional-based ATPG for path delay faults , 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

[8]  Sungho Kang,et al.  Fastpath: a path-delay test generator for standard scan designs , 1994, Proceedings., International Test Conference.

[9]  Sungho Kang,et al.  Path-delay fault simulation for a standard scan design methodology , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[10]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[11]  Vishwani D. Agrawal,et al.  Delay fault models and test generation for random logic sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[12]  Premachandran R. Menon,et al.  Synthesis of Delay-Verifiable Combinational Circuits , 1995, IEEE Trans. Computers.

[13]  John P. Hayes,et al.  Delay fault testing of IP-based designs via symbolic path modeling , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[14]  Sudhakar M. Reddy,et al.  On Multiple Path Propagating Tests for Path Delay Faults , 1991, 1991, Proceedings. International Test Conference.

[15]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[16]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[17]  K. Antreich,et al.  Fast test pattern generation for all path delay faults considering various test classes , 1993, Proceedings ETC 93 Third European Test Conference.