CoARX: A coprocessor for ARX-based cryptographic algorithms
暂无分享,去创建一个
Goutam Paul | Anupam Chattopadhyay | Ayesha Khalid | Zoltán Endre Rákossy | Khawar Shahzad | A. Chattopadhyay | G. Paul | A. Khalid | Z. Rákossy | Khawar Shahzad
[1] Takeshi Sugawara,et al. Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] Ivica Nikolic,et al. Rotational Cryptanalysis of ARX , 2010, FSE.
[3] Yehuda Lindell,et al. Introduction to Modern Cryptography , 2004 .
[4] John Pham,et al. Lightweight Implementations of SHA-3 Candidates on FPGAs , 2011, INDOCRYPT.
[5] Michael Luby,et al. How to Construct Pseudo-Random Permutations from Pseudo-Random Functions (Abstract) , 1986, CRYPTO.
[6] T. Good,et al. Hardware results for selected stream cipher candidates , 2007 .
[7] G. V. Assche,et al. Sponge Functions , 2007 .
[8] Willi Meier,et al. VLSI Characterization of the Cryptographic Hash Function BLAKE , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[9] Patrick Schaumont,et al. ASIC implementations of five SHA-3 finalists , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[10] Yehuda Lindell,et al. Introduction to Modern Cryptography (Chapman & Hall/Crc Cryptography and Network Security Series) , 2007 .
[11] G. Leurent. ARXtools : A toolkit for ARX analysis , 2012 .
[12] Junjie Yan,et al. Hardware Implementation of the Salsa20 and Phelix Stream Ciphers , 2007, 2007 Canadian Conference on Electrical and Computer Engineering.
[13] Stefan Lucks,et al. The Skein Hash Function Family , 2009 .
[14] Muhammad Tariq,et al. Efficient Hardware Implementation of Secure Hash Algorithm (SHA-3) Finalist - Skein , 2011, ICFCE.
[15] Daniel J. Bernstein,et al. The Salsa20 Family of Stream Ciphers , 2008, The eSTREAM Finalists.
[16] Poorvi L. Vora,et al. Analysis of arx round functions in secure hash functions , 2011 .
[17] Marcin Rogawski,et al. Hardware evaluation of eSTREAM Candidates : Grain , Lex , Mickey 128 , Salsa 20 and Trivium , 2007 .
[18] Shoji Miyaguchi,et al. Fast Data Encipherment Algorithm FEAL , 1987, EUROCRYPT.
[19] Samuel Williams,et al. The Landscape of Parallel Computing Research: A View from Berkeley , 2006 .
[20] Deian Stefan,et al. Analysis and Implementation of eSTREAM and SHA-3 Cryptographic Algorithms , 2011 .
[21] Eiji Okamoto,et al. Compact implementations of BLAKE-32 and BLAKE-64 on FPGA , 2010, 2010 International Conference on Field-Programmable Technology.
[22] André DeHon,et al. The Density Advantage of Configurable Computing , 2000, Computer.
[23] Stefan Tillich. Hardware Implementation of the SHA-3 Candidate Skein , 2009, IACR Cryptol. ePrint Arch..
[24] Bart Preneel,et al. Toolkit for the Differential Cryptanalysis of ARX-based Cryptographic Constructions , 2010 .
[25] Christina Boura,et al. Side-Channel Analysis of Grøstl and Skein , 2012, 2012 IEEE Symposium on Security and Privacy Workshops.
[26] Eiji Okamoto,et al. Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[27] Jean-Philippe Aumasson,et al. Tuple cryptanalysis of ARX with application to BLAKE and Skein , 2011 .
[28] Patrick Schaumont,et al. Design and benchmarking of an ASIC with five SHA-3 finalist candidates , 2013, Microprocess. Microsystems.
[29] Andreas Peter Burg,et al. Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture , 2012, IACR Cryptol. ePrint Arch..
[30] N. Felber,et al. VLSI hardware evaluation of the stream ciphers Salsa20 and ChaCha, and the compression function Rumba , 2008, 2008 2nd International Conference on Signals, Circuits and Systems.
[31] Samuel Neves,et al. Cryptography in GPUs , 2009 .
[32] François Durvaux,et al. Compact FPGA Implementations of the Five SHA-3 Finalists , 2011, CARDIS.
[33] Subhamoy Maitra,et al. Designing high-throughput hardware accelerator for stream cipher HC-128 , 2012, 2012 IEEE International Symposium on Circuits and Systems.
[34] Jarrod A. Roy,et al. EPIC: Ending Piracy of Integrated Circuits , 2008, 2008 Design, Automation and Test in Europe.
[35] Kazuo Ohta,et al. Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII , 2010, IACR Cryptol. ePrint Arch..
[36] Kris Gaj,et al. Comparison of hardware performance of selected Phase II eSTREAM candidates , 2007 .