Efficient Approximation Algorithms for Minimum Enclosing Convex Shapes

A data processing system includes logic to ensure result data stored in a history buffer is in a correct chronological order and is not overwritten until an appropriate point in time. The logic also ensures that the history buffer is able to capture result data that is produced with unexpected delays. The history buffer entries act as a "backup" for an architected register by storing older result data and rely on unique target identifiers assigned to dispatched instructions to keep the result data in a correct chronological order. Furthermore, a target identifier field of the architected register holds the latest target identifier assigned to a youngest instruction that modifies the architected register. Additionally, previous result data in the register is backed up in an allocated history buffer entry. If the result data is not yet available, the target identifier in the register will be deposited in the target identifier field of the history buffer entry. One timing cycle before a result data value is expected to be available, a target identifier assigned to the instruction producing the data is broadcast on the Result bus. If the result data is delayed at a next timing cycle, a re-execute signal is asserted on the Result bus to notify a history buffer entry or a register that the data is not ready to be stored therein. Furthermore, the re-execute signal remains asserted until the result data is available. During the same cycle, the re-execute signal is negated, result data is presented on the Result bus. A functional unit that broadcasts an asserted re-execute signal after it broadcasts a first target identifier, can broadcast a second target identifer before the re-execute signal is negated.