Model-Based Virtual Prototype Acceleration
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[1] Christian Haubelt,et al. Electronic System-Level Synthesis Methodologies , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Christian Haubelt,et al. Mapping Actor-Oriented Models to TLM Architectures , 2007, FDL.
[3] Wen-Chuan Lee,et al. Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[4] Jürgen Teich,et al. Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs , 2012, 17th Asia and South Pacific Design Automation Conference.
[5] Sandeep K. Shukla,et al. A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design , 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..
[6] Rolf Drechsler,et al. System exploration of SystemC designs , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).
[7] L. Thiele,et al. Symbolic model checking of process networks using interval diagram techniques , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[8] Alper Sen,et al. Concurrency-oriented verification and coverage of system-level designs , 2011, TODE.
[9] Franco Fummi,et al. LAERTE++: an Object Oriented High-level TPG for SystemC Designs , 2003, FDL.
[10] Edward A. Lee,et al. A framework for comparing models of computation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Axel Jantsch,et al. Models of computation and languages for embedded system design , 2005 .
[12] Robert K. Brayton,et al. Algorithms for discrete function manipulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[13] Florence Maraninchi,et al. LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level , 2005, Des. Autom. Embed. Syst..
[14] James C. Hoe,et al. Operation-centric hardware description and synthesis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Frank Ghenassia. Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .
[16] Stephen A. Edwards,et al. Design of embedded systems: formal models, validation, and synthesis , 1997, Proc. IEEE.
[17] Florence Maraninchi,et al. A SystemC/TLM Semantics in Promelaand Its Possible Applications , 2007, SPIN.
[18] Rainer Leupers,et al. Virtual Manycore platforms: Moving towards 100+ processor cores , 2011, 2011 Design, Automation & Test in Europe.
[19] Sofia Cassel,et al. Graph-Based Algorithms for Boolean Function Manipulation , 2012 .
[20] Roberto Passerone,et al. A Platform-Based Taxonomy for ESL Design , 2006, IEEE Design & Test of Computers.
[21] Sandeep K. Shukla,et al. Translating concurrent action oriented specifications to synchronous guarded actions , 2010, LCTES '10.
[22] Alberto L. Sangiovanni-Vincentelli,et al. System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] Fabrizio Ferrandi,et al. Functional verification for SystemC descriptions using constraint solving , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[24] Christian Haubelt,et al. Automatic generation of system-level virtual prototypes from streaming application models , 2011, 2011 22nd IEEE International Symposium on Rapid System Prototyping.
[25] Axel Jantsch,et al. System modeling and transformational design refinement in ForSyDe [formal system design] , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[26] Sanjai Rayadurgam,et al. Auto-generating Test Sequences Using Model Checkers: A Case Study , 2003, FATES.
[27] Sander Stuijk,et al. Minimising buffer requirements of synchronous dataflow graphs with model checking , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[28] Alain Greiner,et al. Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[29] Jörg Desel,et al. ''What Is a Petri Net?'' , 2001, Unifying Petri Nets.
[30] Jürgen Teich,et al. FunState —an internal design representation for codesign , 1999, ICCAD 1999.
[31] Edward A. Lee,et al. Synthesis of Embedded Software from Synchronous Dataflow Specifications , 1999, J. VLSI Signal Process..
[32] Edmund M. Clarke,et al. Efficient generation of counterexamples and witnesses in symbolic model checking , 1995, DAC '95.
[33] Edmund M. Clarke,et al. Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..
[34] Christian Haubelt,et al. Efficient Representation and Simulation of Model-Based Designs , 2006, FDL.
[35] Daniel Kroening,et al. Race analysis for SystemC using model checking , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[36] Martin Radetzki,et al. Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling , 2009, IESS.
[37] Michael K. Molloy,et al. Petri net , 2003 .