Design intent coverage revisited

Design intent coverage is a formal methodology for analyzing the gap between a formal architectural specification of a design and the formal functional specifications of the component RTL blocks of the design. In this article we extend the design intent coverage methodology to hybrid specifications containing both state-machines and formal properties. We demonstrate the benefits of this extension in two domains of considerable recent interest, namely (a) the use of auxiliary state-machines in formal specifications, and (b) the use of modest sized RTL blocks in the design intent coverage analysis.

[1]  Ivo Bolsens,et al.  Proceedings of the conference on Design, Automation & Test in Europe , 2000 .

[2]  Timothy Kam,et al.  Coverage estimation for symbolic model checking , 1999, DAC '99.

[3]  Pallab Dasgupta,et al.  What lies between Design Intent Coverage and Model Checking? , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[4]  Robert P. Kurshan,et al.  A Practical Approach to Coverage in Model Checking , 2001, CAV.

[5]  Orna Kupferman,et al.  Coverage metrics for formal verification , 2003, International Journal on Software Tools for Technology Transfer.

[6]  Orna Grumberg,et al.  "Have I written enough Properties?" - A Method of Comparison between Specification and Implementation , 1999, CHARME.

[7]  Pallab Dasgupta,et al.  A Roadmap for Formal Property Verification , 2006 .

[8]  Hai Zhou,et al.  Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems , 2010 .

[9]  Orna Kupferman,et al.  Coverage Metrics for Temporal Logic Model Checking , 2001, TACAS.

[10]  A. Prasad Sistla,et al.  The complexity of propositional linear temporal logics , 1982, STOC '82.

[11]  Orna Kupferman,et al.  Coverage metrics for temporal logic model checking* , 2006, Formal Methods Syst. Des..

[12]  Ansuman Banerjee,et al.  Design-Intent Coverage - A New Paradigm for Formal Property Verification , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Edmund M. Clarke,et al.  Model Checking , 1999, Handbook of Automated Reasoning.