A CMOS square-law programmable floating resistor
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A CMOS architecture for a floating linear resistor which exploits the square-law model of the MOS transistor is presented. The architecture is programmable by a DC control voltage, and it is fabricated in a 2-/spl mu/m p-well CMOS MOSIS process. The resistor occupies 210 /spl mu/m /spl times/ 270 /spl mu/m, consumes .4-4 mW with /spl plusmn/5 V supply and exhibits a signal-to-noise-ratio (at1% total harmonic distortion) of more than 100 dB over a 1-V range of the DC control voltage.<<ETX>>
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