论文信息 - High performance 20-30 V LDMOS transistors in a 0.65 /spl mu/m-based BiCMOS compatible process

High performance 20-30 V LDMOS transistors in a 0.65 /spl mu/m-based BiCMOS compatible process

A 5th generation SMARTMOS/sup TM/ 0.65 /spl mu/m BiCMOS technology geared for advanced power applications yields the lowest specific on-resistance reported to date for the 20-30 V breakdown voltage range. A specific on-resistance of 0.34 m/spl Omega/-cm/sup 2/ is achieved (V/sub GS/=10 V) for an avalanche breakdown voltage of 27 V. Experimental results are compared with numerical simulation and prior results in the literature. The effects of metal debiasing are also characterized.

P. Hui | Rainer Thoma | R. Baird | J. Victory | S. Merchant

[1] H.-T. Yuan,et al. Optimized 25 V, 0.34 m/spl Omega//spl middot/cm/sup 2/ very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS process , 1996, International Electron Devices Meeting. Technical Digest.

[2] Young-June Park,et al. Two-dimensional device simulation program: 2DP , 1985 .

[3] P. Galbiati,et al. A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts , 1986, IEEE Transactions on Electron Devices.

[4] Taylor R. Efland,et al. A performance comparison between new reduced surface drain "RSD" LDMOS and RESURF and conventional planar power devices rated at 20 V , 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.