Combinatorial Logic Circuitry as Means to Protect Low Cost Devices Against Side Channel Attacks

In this paper we present a clock frequency watch dog that can be realized using a digital standard CMOS library. Such watch dog is required to prevent clock speed manipulations that can support side channel attacks on cryptographic hardware devices. The additional area and power consumed by the watch dog for an AES hardware accelerator are 4,200µm2 and 2nJ per 128 bit respectively. The physical properties and the use of standard CMOS technology ensure extremely low additional production cost. Thus, our approach is very well suited to improve the security of low cost devices such as wireless sensor nodes.

[1]  Chae Hoon Lim,et al.  Information Security and Cryptology — ICISC 2002 , 2003, Lecture Notes in Computer Science.

[2]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[3]  Neal Koblitz,et al.  Advances in Cryptology — CRYPTO ’96 , 2001, Lecture Notes in Computer Science.

[4]  George S. Taylor,et al.  Security Evaluation of Asynchronous Circuits , 2003, CHES.

[5]  Paul C. Kocher,et al.  Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.

[6]  David Naccache,et al.  Cryptographic Hardware and Embedded Systems — CHES 2001 , 2001 .

[7]  Hervé Chabanne,et al.  Electromagnetic Side Channels of an FPGA Implementation of AES , 2004, IACR Cryptol. ePrint Arch..

[8]  Peter Wright,et al.  Spy Catcher : The Candid Autobiography of a Senior Intelligence Officer , 1987 .

[9]  Christophe Giraud,et al.  An Implementation of DES and AES, Secure against Some Attacks , 2001, CHES.

[10]  Wim van Eck,et al.  Electromagnetic radiation from video display units: An eavesdropping risk? , 1985, Comput. Secur..

[11]  William M. Daley,et al.  Security Requirements for Cryptographic Modules , 1999 .

[12]  Peter Langendörfer,et al.  An Area Efficient Realisation of AES for Wireless Devices (Eine flächeneffiziente AES Hardwarerealisierung für drahtlose Geräte) , 2007, it Inf. Technol..

[13]  Bart Preneel,et al.  Power-analysis attack on an ASIC AES implementation , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[14]  Ingrid Verbauwhede,et al.  Design method for constant power consumption of differential logic circuits , 2005, Design, Automation and Test in Europe.

[15]  Michael Wiener,et al.  Advances in Cryptology — CRYPTO’ 99 , 1999 .

[16]  Johannes Blömer,et al.  Provably Secure Masking of AES , 2004, IACR Cryptol. ePrint Arch..

[17]  Peter Langendörfer,et al.  Scenario Definition and Initial Threat Analysis , 2006 .

[18]  Stefan Mangard,et al.  Successfully Attacking Masked AES Hardware Implementations , 2005, CHES.

[19]  Berk Sunar,et al.  Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings , 2005, CHES.

[20]  Stefan Mangard,et al.  A Simple Power-Analysis (SPA) Attack on Implementations of the AES Key Expansion , 2002, ICISC.