A 15-Gb / s 2 : 1 Multiplexer in 0 . 18-m CMOS

By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18m CMOS process. With a power consumption of 110 mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15 Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225 mV and a root-mean-square jitter of 2.7 ps.