Power and thermal challenges for microprocessor architectures

Power dissipation has become a critical design constraint for a wide range of electronics design: from high-performance microprocessor architectures to much smaller embedded systems. The demand for more sophisticated and faster computation, along with supply voltage scaling limitations are among the main driving forces behind the power dissipation increase. As a result, optimization techniques that target power and temperature need to be incorporated at every stage of the design process, from the operating system and architecture level, to behavioral synthesis and circuit level. In this thesis we propose and investigate the effectiveness of power and temperature optimization techniques at various abstraction levels targeting microprocessor architectures and embedded systems design flow. We look at circuit level power reduction through effective distribution of the existing slack formulated as a budgeting problem. Our experimental analysis reveals 15% improvement in average power and 18% in maximum power consumption over MCNC benchmark set. For behavioral synthesis we investigate low power scheduling selection. We demonstrate that the decisions made at higher levels of abstraction such as behavioral synthesis have significant impact on the design space of the following stages. Moreover, in some cases the design space restrictions are unintentional and undetected. We propose a metric-based evaluation technique that reduces the on-chip temperatures by 12°C on average for data flow graphs extracted from the MediaBench Suite. At the architecture-level we explore the benefits of hierarchical and factored architectures in reducing the power waste due to sub-optimal processor resource sizes. Our analysis indicates power savings around 20% for such architectures. Furthermore, an additional 13% reduction is also possible through adapting the processor resources to the application phase behavior. By minimizing the sizes of performance enhancing structures on the critical path and utilizing hierarchical extensions to extract the distant ILP, it is possible to improve the microprocessor thermal profile. We observed 86% reduction in the number of cycles over the critical temperature threshold. Using this framework, we propose a reduced-overhead activity migration scheme. As a result of the data buffering in shared structures, thermally-triggered activity migration outperforms other dynamic thermal management techniques such as idealized dynamic frequency scaling and global clock gating. Finally, we investigate operating system level thermal management on a Power4-like architecture. We analyze the effects of thread selection on processor temperature, by utilizing the already existing thread scheduling infrastructure. Scheduling decisions are based on dynamic thermal profiling of threads and temperature readings from on-chip sensors. Our MinTemp scheduling policy yields only 3% cycles above the threshold, with virtually no performance degradation over thermally challenging SPEC2000 benchmark suite.