General purpose neuroemulator architecture: design and VHDL simulation

A new SIMD architecture for artificial neural network emulation, based on bus segmentation, is proposed. As demonstration, we implement on this architecture the well known multilayer perceptron with backpropagation learning. VHDL simulations are carried out, being compared to simulations on a general purpose computer. System scalability (performance in relation to the number of processing units included) is analysed. This architecture is being now implemented by means of FPGA devices; results for an arithmetic unit are already provided.

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