A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length
暂无分享,去创建一个
J. Zhao | T. Grider | J.P. Lu | Y. Xu | D. Mercer | D. Miles | A. Gurba | C. Lin | M. Hewson | J. Ruan | L. Tsung | R. Kuan | C. Montgomery
[1] Qi Xiang,et al. 15 nm gate length planar CMOS transistor , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[2] K. Fujihara,et al. CMOS device scaling beyond 100 nm , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[3] G. Dewey,et al. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[4] Hiroshi Iwai,et al. NiSi salicide technology for scaled CMOS , 2002 .
[5] H. Bender,et al. Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies , 2001 .