The timing control circuit unit

PROBLEM TO BE SOLVED: To prevent deterioration of jitter performance affected by manufacturing process dispersion, power source voltage fluctuation, temperature change or input signal jitter in a hierarchical structure having at least two timing control circuits for improving jitter performance of a clock signal generator. SOLUTION: This timing control circuit is composed of at least two hierarchical timing control circuits and at least one conversion circuit. The first hierarchical timing control circuit roughly adjusts a clock phase, and the second hierarchical timing control circuit finely adjusts the clock phase. A delay match circuit outputs a control signal for aligning as identical delay time, unit delay time of a rough delay circuit column provided to the first timing control circuit for rough adjustment and whole delay time of a fine delay circuit column provided to the second timing control circuit for fine adjustment. COPYRIGHT: (C)2004,JPO