A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2Mbps, with an area occupancy of 46%, due to the efficient resources reuse.

[1]  Ji Won Jung,et al.  FPGA realization of adaptive coding rate trellis-coded 8PSK system , 2003, 14th IEEE Proceedings on Personal, Indoor and Mobile Radio Communications, 2003. PIMRC 2003..

[2]  Joseph Mitola,et al.  Technical challenges in the globalization of software radio , 1999, IEEE Commun. Mag..

[3]  Tughrul Arslan,et al.  Domain specific reconfigurable fabric targeting Viterbi algorithm , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[4]  J.R. Cavallaro,et al.  A reconfigurable Viterbi decoder architecture , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[5]  Dennis Goeckel,et al.  A reconfigurable, power-efficient adaptive Viterbi decoder , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Chao Du,et al.  An adaptive Viterbi decoder based on FPGA dynamic reconfiguration technology , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[7]  Peter Grant,et al.  Digital Communications (3rd edition) , 2009 .

[8]  Ran-Hong Yan,et al.  A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[9]  J.E. Mazo,et al.  Digital communications , 1985, Proceedings of the IEEE.

[10]  Trieu-Kien Truong,et al.  A VLSI design for a trace-back Viterbi decoder , 1992, IEEE Trans. Commun..

[11]  Jr. G. Forney,et al.  Viterbi Algorithm , 1973, Encyclopedia of Machine Learning.

[12]  M. Omair Ahmad,et al.  A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[13]  Tae-Jin Kim,et al.  High performance Viterbi decoder using modified register exchange methods , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[14]  Mohamed I. Elmasry,et al.  Low-power register-exchange Viterbi decoder for high-speed wireless communications , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[15]  Mark Cummings,et al.  FPGA in the software radio , 1999, IEEE Commun. Mag..

[16]  M. Omair Ahmad,et al.  FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.