S/W, H/W co-simulation 위한 저전력 Deblocking filter 구조 설계

This paper supposed a blocking filer architecture for S/W H/W co-simulations. We redesign some member functions in loopfiler class that include JSVM reference software and design H/W loopfilter block base on redesigned loopfilter class architecture. Then, we use output vectors of redesigned member functions's to verification for H/W blocks. also, We propose low-power scheme for this H/W architecture.