A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

An architecture for enabling self-authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints obtained by offset-superimposing six out of one thousand 4 Kb domains randomly chosen in 4 Mb embedded DRAM. Authentication is accomplished by regenerating various encrypted intrinsic fingerprints, which are then compared with the bit strings in the eFUSE. Monte Carlo simulations demonstrate that, targeting an average of 32 retention fails per domain, the strings are unique and authentication is statistically guaranteed without bit correction even when unstable bits are introduced. The preliminary results are confirmed in > 50 parts containing 4 Mb memory implemented in 22-nm SOI hardware under the target voltage ±10% conditions. The analytical model predicts > 10 20 years to crack the encryption by brute force, while satisfying > 99.9999% successful authentication for one million parts.

[1]  Balaram Sinharoy,et al.  POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor , 2011, IEEE Journal of Solid-State Circuits.

[2]  Subramanian S. Iyer,et al.  Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM , 2013, IEEE Journal of Solid-State Circuits.

[3]  Ying Su,et al.  A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Kris Gaj,et al.  Lessons Learned from Designing a 65 nm ASIC for Evaluating Third Round SHA-3 Candidates , 2012 .

[5]  Brian Reed,et al.  A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Daniel E. Holcomb,et al.  Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers , 2009, IEEE Transactions on Computers.

[7]  Stephen A. Benton,et al.  Physical one-way functions , 2001 .

[8]  Srivatsan Chellappa,et al.  Improved circuits for microchip identification using SRAM mismatch , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[9]  Raj Chakraborty,et al.  Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistors , 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

[10]  高野 勝男.  The Hypergeometric Series and Trigonometric Sums (単葉関数論における係数不等式とその周辺 短期共同研究報告集) , 2005 .

[11]  Mario Konijnenburg,et al.  Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[12]  Subramanian S. Iyer,et al.  Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[13]  C. Kothandaraman,et al.  3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[14]  John Kelsey,et al.  Third-Round Report of the SHA-3 Cryptographic Hash Algorithm Competition , 2012 .

[15]  Srinivas Devadas,et al.  Performance metrics and empirical results of a PUF cryptographic key generation ASIC , 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

[16]  S. Narasimha,et al.  22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL , 2012, 2012 International Electron Devices Meeting.