Most hardware "true" random number generators (TRNGs) take advantage of the thermal agitation around a flip-flop metastable state. In field programmable gate arrays (FPGAs), the classical TRNG structure uses two clocks, either from a PLL or from ring oscillators, in order to sample one by the other. This creates good TRNGs albeit limited in frequency by the interference rate which cannot exceed a few Mbit/s. This article presents an architecture allowing higher bit rates while maintaining provable unconditional security. This requirement becomes stringent for secure communication applications such as the cryptographic quantum key distribution (QKD) protocols. The proposed architecture is very simple as it is based on an open loop structure without any specific component such as PLLs.
[1]
Hendrikus J. M. Veendrick,et al.
The behaviour of flip-flops used as synchronizers and prediction of their failure rate
,
1980
.
[2]
Milos Drutarovský,et al.
True Random Number Generator Embedded in Reconfigurable Hardware
,
2002,
CHES.
[3]
Lee-Sup Kim,et al.
Metastability of CMOS latch/flip-flop
,
1990
.
[4]
Miss A.O. Penney.
(b)
,
1974,
The New Yale Book of Quotations.
[5]
E. G. Chester,et al.
Design of an on–chip random number generator using metastability
,
2002,
Proceedings of the 28th European Solid-State Circuits Conference.
[6]
Kris Gaj,et al.
An embedded true random number generator for FPGAs
,
2004,
FPGA '04.