Fault tolerance in VLSI circuits
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[1] José A. B. Fortes,et al. A taxonomy of reconfiguration techniques for fault-tolerant processor arrays , 1990, Computer.
[2] Stuart K. Tewksbury,et al. Wafer-level integrated systems : implementation issues , 1989 .
[3] G. Grisetti,et al. Further Reading , 1984, IEEE Spectrum.
[4] J. F. McDonald,et al. The trials of wafer-scale integration: Although major technical problems have been overcome since WSI was first tried in the 1960s, commercial companies can't yet make it fly , 1984, IEEE Spectrum.
[5] C.H. Stapper,et al. Integrated circuit yield statistics , 1983, Proceedings of the IEEE.
[6] D. Patterson,et al. Wafer scale integration , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[7] W.R. Moore,et al. A review of fault-tolerant techniques for the enhancement of integrated circuit yield , 1986, Proceedings of the IEEE.
[8] R. G. Nelson,et al. Laser programmable redundancy and yield improvement in a 64K DRAM , 1981 .
[9] T.P. Haraszti. A novel associative approach for fault-tolerant MOS RAMs , 1982, IEEE Journal of Solid-State Circuits.
[10] C. H. Stapper,et al. Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..
[11] I. Koren. The Effect of Scaling on the Yield of VLSI Circuits , 1988 .
[12] Melvin A. Breuer,et al. On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays , 1984, IEEE Transactions on Computers.
[13] Israel Koren. A reconfigurable and fault-tolerant VLSI multiprocessor array , 1981, ISCA '81.
[14] Adit D. Singh. Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays , 1988, IEEE Trans. Computers.
[15] Duncan M. Walker. Yield simulation for integrated circuits , 1987 .
[16] P. W. Wyatt,et al. Restructurable VLSI-a demonstrated wafer-scale technology , 1989, [1989] Proceedings International Conference on Wafer Scale Integration.
[17] Israel Koren,et al. Yield Models for Defect-Tolerant VLSI Circuits: A Review , 1989 .
[18] Chin-Long Wey. On yield consideration for the design of redundant programmable logic arrays , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Norbert Wehn,et al. Defect Tolerance in a 16-Bit Microprocessor , 1989 .
[20] W. Kent Fuchs,et al. Diagnosis and Repair of Large Memories: A Critical Review and Recent Results , 1989 .
[21] Dhiraj K. Pradhan,et al. Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay , 1988 .