Characterizing processor thermal behavior

Temperature is a dominant factor in the performance, reliability, and leakage power consumption of modern processors. As a result, increasing numbers of researchers evaluate thermal characteristics in their proposals. In this paper, we measure a real processor focusing on its thermal characterization executing diverse workloads. Our results show that in real designs, thermal transients operate at larger scales than their performance and power counterparts. Conventional thermal simulation methodologies based on profile-based simulation or statistical sampling, such as Simpoint, tend to explore very limited execution spans. Short simulation times can lead to reduced matchings between performance and thermal phases. To illustrate these issues we characterize and classify from a thermal standpoint SPEC00 and SPEC06 applications, which are traditionally used in the evaluation of architectural proposals. This paper concludes with a list of recommendations regarding thermal modeling considerations based on our experimental insights.

[1]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[2]  Gregory A. Northrop,et al.  Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors , 1999, IBM Journal of Research and Development.

[3]  Yiu-Hing Chan,et al.  Power-constrained high-frequency circuits for the IBM POWER6 microprocessor , 2007, IBM J. Res. Dev..

[4]  Kevin Skadron,et al.  Many-core design from a thermal perspective , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[5]  Kia Bazargan,et al.  Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction , 2008, ICCAD 2008.

[6]  Gregory A. Northrop,et al.  Chip integration methodology the IBM , 1999 .

[7]  Taewhan Kim,et al.  Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension , 2008, 2008 Asia and South Pacific Design Automation Conference.

[8]  Sarita V. Adve,et al.  AS SCALING THREATENS TO ERODE RELIABILITY STANDARDS, LIFETIME RELIABILITY MUST BECOME A FIRST-CLASS DESIGN CONSTRAINT. MICROARCHITECTURAL INTERVENTION OFFERS A NOVEL WAY TO MANAGE LIFETIME RELIABILITY WITHOUT SIGNIFICANTLY SACRIFICING COST AND PERFORMANCE , 2005 .

[9]  Brad Calder,et al.  Automatically characterizing large scale program behavior , 2002, ASPLOS X.

[10]  R. Mukherjee,et al.  Thermal Sensor Allocation and Placement for Reconfigurable Systems , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[11]  Jose Renau,et al.  Cooling solutions for processor Infrared Thermography , 2010, 2010 26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

[12]  Nicholas Nethercote,et al.  Valgrind: a framework for heavyweight dynamic binary instrumentation , 2007, PLDI '07.

[13]  Sachin S. Sapatnekar,et al.  Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and Transient Analysis , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[14]  Tajana Simunic,et al.  Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors , 2009, SIGMETRICS '09.

[15]  Krste Asanovic,et al.  Reducing power density through activity migration , 2003, ISLPED '03.

[16]  Margaret Martonosi,et al.  Phase characterization for power: evaluating control-flow-based and event-counter-based techniques , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[17]  Lizy Kurian John,et al.  Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite , 2007, ISCA '07.

[18]  Kevin Skadron,et al.  Differentiating the roles of IR measurement and simulation for power and temperature-aware design , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[19]  Lieven Eeckhout,et al.  Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites , 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..

[20]  Jose Renau,et al.  Power model validation through thermal measurements , 2007, ISCA '07.

[21]  Seda Ogrenci Memik,et al.  Systematic temperature sensor allocation and placement for microprocessors , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[22]  Brad Calder,et al.  Phase tracking and prediction , 2003, ISCA '03.

[23]  Yao-Wen Chang,et al.  Joint exploration of architectural and physical design spaces with thermal consideration , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[24]  James E. Smith,et al.  Comparing program phase detection techniques , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[25]  J. Wakil,et al.  Spatially-resolved imaging of microprocessor power (SIMP): hotspots in microprocessors , 2006, Thermal and Thermomechanical Proceedings 10th Intersociety Conference on Phenomena in Electronics Systems, 2006. ITHERM 2006..

[26]  S Jarp,et al.  Perfmon2: a leap forward in performance monitoring , 2008 .

[27]  Gu-Yeon Wei,et al.  Thread motion: fine-grained power management for multi-core systems , 2009, ISCA '09.